View R5F21113DFP_1278109.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

renesas 16-bit single-chip microcomputer m16c family/r8c/tiny series r8c/11 group 16 rev. 1.20 revision date: jan 27, 2006 hardware manual www.renesas.com rej09b0062-0120 all information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by renesas technology corp. without notice. please review the latest information published by renesas technology corp. through various means, including the renesas technology corp. website (http://www.renesas.com).
keep safety first in your circuit designs! notes regarding these materials 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, pro- grams, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers con- tact renesas technology corp. or an authorized renesas technology corp. product dis- tributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by vari- ous means, including the renesas technology corp. semiconductor home page (http:// www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liabil- ity or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or repro- duce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein.
how to use this manual 1. introduction this hardware manual provides detailed information on the r8c/11 group of microcomputers. users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. register diagram the symbols, and descriptions, used for bit function in each register are shown below. *1 blank:set to ??or ??according to the application 0: set to ? 1: set to ? x: nothing is assigned *2 rw: read and write ro: read only wo: write only ? : nothing is assigned *3 ? reserved bit reserved bit. set to specified value. *4 ? nothing is assigned nothing is assigned to the bit concerned. as the bit may be use for future functions, set to ??when writing to this bit. ? do not set to this value the operation is not guaranteed when a value is set. ? function varies depending on mode of operation bit function varies depending on peripheral function mode. refer to respective register for each mode. *5 follow the text in each manual for binary and hexadecimal notations. *4 x x x r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t x x xx x x0 0 h bit name bit symbol rw b 7b 6b 5b 4b 3b2b 1b 0 x x x b i t 1 0 : x x x 0 1 : x x x 1 0 : a v o i d t h i s s e t t i n g 1 1 : x x x b 1 b 0 xxx1 x x x 0 xxx4 r e s e r v e d b i t xxx5 x x x 7 x x x 6 function n o t h i n g i s a s s i g n e d . w h e n w r i t e , s h o u l d s e t t o " 0 " . w h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e . xxx bit function varies depending on each operation mode must set to 0 0 ( b 3 ) (b2) rw rw rw r w w o r w ro x x x b i t 0: xxx 1: xxx *1 *2 *3 *5
document 3. m16c family documents the following documents were prepared for the m16c family. (1) contents short sheet data sheet hardware manual software manual application note renesas technical update hardware overview hardware overview and electrical characteristics hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, timing charts). *refer to the application note for how to use peripheral functions. detailed description of assembly instructions and microcomputer performance of each instruction usage and application examples of peripheral functions sample programs introduction to the basic functions in the m16c family programming method with assembly and c languages preliminary report about the specification of a product, a document, etc. notes: 1. before using this material, please visit the our website to verify that this is the most updated document available.
a-1 table of contents sfr page reference chapter 1. overview .............................................................. 1 1.1 applications ............................................................................................................... ..... 1 1.2 performance overview ................................................................................................... 2 1.3 block diagram .............................................................................................................. .. 3 1.4 product information ....................................................................................................... 4 1.5 pin assignments............................................................................................................ .5 1.6 pin description ............................................................................................................ ... 6 chapter 2. central processing unit (cpu) .......................... 7 2.1 data registers (r0, r1, r2 and r3) .............................................................................. 7 2.2 address registers (a0 and a1) ..................................................................................... 8 2.3 frame base register (fb) .............................................................................................. 8 2.4 interrupt table register (intb)...................................................................................... 8 2.5 program counter (pc) .................................................................................................... 8 2.6 user stack pointer (usp) and interrupt stack pointer (isp) ...................................... 8 2.7 static base register (sb) .............................................................................................. 8 2.8 flag register (flg) ........................................................................................................ 8 2.8.1 carry flag (c flag) .................................................................................................... 8 2.8.2 debug flag (d flag) ................................................................................................... 8 2.8.3 zero flag (z flag) ..................................................................................................... .8 2.8.4 sign flag (s flag) ..................................................................................................... .8 2.8.5 register bank select flag (b flag) .......................................................................... 8 2.8.6 overflow flag (o flag) .............................................................................................. 8 2.8.7 interrupt enable flag (i flag) .................................................................................... 8 2.8.8 stack pointer select flag (u flag) ........................................................................... 8 2.8.9 processor interrupt priority level (ipl) .................................................................. 8 2.8.10 reserved area......................................................................................................... .8 chapter 3. memory ................................................................ 9 chapter 4. special function registers (sfr) ................... 10 chapter 5. reset .................................................................. 14 5.1 hardware reset ............................................................................................................ 1 4 5.1.1 hardware reset 1 ......................................................................................................... ......................... 14 5.1.2 hardware reset 2 ......................................................................................................... ......................... 17 5.1.3 power-on reset function .................................................................................................. ................... 18 5.2 software reset ............................................................................................................. .20 5.3 watchdog timer reset ................................................................................................. 20
a-2 5.4 voltage detection circuit ............................................................................................. 21 5.4.1 voltage detection interrupt .............................................................................................. .................... 26 5.4.2 exiting stop mode on a voltage detection interrupt ....................................................................... .. 28 chapter 6. clock generation circuit.................................. 29 6.1 main clock ................................................................................................................. .... 34 6.2 on-chip oscillator clock ............................................................................................. 35 6.2.1 low-speed on-chip oscillator ............................................................................................. ............... 35 6.2.2 high-speed on-chip oscillator ............................................................................................ ............... 35 6.3 cpu clock and peripheral function clock ................................................................ 36 6.3.1 cpu clock ................................................................................................................ .............................. 36 6.3.2 peripheral function clock (f 1 , f 2 , f 8 , f 32 , f ad , f 1sio , f 8sio , f 32sio ) ....................................................... 36 6.3.3 f ring and f ring128 ........................................................................................................................ ........................................... 36 6.3.4 f ring-fast ...................................................................................................................... ................................................................ 36 6.4 power control .............................................................................................................. .37 6.4.1 normal operation mode .................................................................................................... ................... 37 6.4.2 wait mode ................................................................................................................ .............................. 39 6.4.3 stop mode ................................................................................................................ .............................. 40 6.5 oscillation stop detection function ........................................................................... 42 6.5.1 how to use oscillation stop detection function ........................................................................... ... 42 chapter 7. protection .......................................................... 44 chapter 8. processor mode ................................................ 45 8.1 types of processor mode ............................................................................................ 45 chapter 9. bus ..................................................................... 46 chapter 10. interrupt ........................................................... 47 10.1 interrupt overview ...................................................................................................... 47 10.1.1 type of interrupts ...................................................................................................... .......................... 47 10.1.2 software interrupts ..................................................................................................... ........................ 48 10.1.3 hardware interrupts ..................................................................................................... ....................... 49 10.1.4 interrupts and interrupt vector ......................................................................................... ................. 50 10.1.5 interrupt control ....................................................................................................... .......................... 52 ______ 10.2 int interrupt ............................................................................................................. ... 60 ________ 10.2.1 int0 interrupt .......................................................................................................... ............................ 60 _______ 10.2.2 int0 input filter ....................................................................................................... ............................ 61 ______ ______ 10.2.3 int1 interrupt and int2 interrupt ....................................................................................... ............... 62 ______ 10.2.4 int3 interrupt .......................................................................................................... ............................ 63 10.3 key input interrupt ..................................................................................................... 65 10.4 address match interrupt ............................................................................................ 66 chapter 11. watchdog timer .............................................. 68 chapter 12. timers .............................................................. 70 12.1 timer x ................................................................................................................... ..... 71 12.1.1 timer mode .............................................................................................................. ............................ 73
a-3 12.1.2 pulse output mode ....................................................................................................... ...................... 74 12.1.3 event counter mode ...................................................................................................... ..................... 75 12.1.4 pulse width measurement mode ............................................................................................ ........... 76 12.1.5 pulse period measurement mode .......................................................................................... ........... 78 12.2 timer y................................................................................................................... ...... 80 12.2.1 timer mode .............................................................................................................. ............................ 83 12.2.2 programmable waveform generation mode ................................................................................... .85 12.3 timer z ................................................................................................................... ...... 88 12.3.1 timer mode .............................................................................................................. ............................ 91 12.3.2 programmable waveform generation mode ................................................................................... .93 12.3.3 programmable one-shot generation mode ................................................................................... ... 95 12.3.4 programmable wait one-shot generation mode ............................................................................. 9 8 12.4 timer c ................................................................................................................... ... 101 12.4.1 input capture mode ..................................................................................................... .................... 105 12.4.2 output compare mode .................................................................................................... ................ 107 chapter 13. serial interface .............................................. 109 13.1 clock synchronous serial i/o mode ....................................................................... 114 13.1.1 polarity select function ................................................................................................ ................... 117 13.1.2 lsb first/msb first select function ..................................................................................... ......... 117 13.1.3 continuous receive mode ................................................................................................. .............. 118 13.2 clock asynchronous serial i/o (uart) mode ....................................................... 119 13.2.1 txd10/rxd1 select function (uart1) ...................................................................................... ...... 122 13.2.2 txd11 select function (uart1) ........................................................................................... ........... 122 13.2.3 bit rate ................................................................................................................ .............................. 123 chapter 14. a/d converter................................................ 124 14.1 one-shot mode ......................................................................................................... 128 14.2 repeat mode ............................................................................................................. 13 0 14.3 sample and hold ...................................................................................................... 132 14.4 a/d conversion cycles ........................................................................................... 132 14.5 internal equivalent circuit of analog input ........................................................... 133 14.6 inflow current bypass circuit ................................................................................ 134 14.7 output impedance of sensor under a/d conversion........................................... 135 chapter 15. programmable i/o ports .............................. 137 15.1 description ............................................................................................................... . 137 15.1.1 port pi direction register (pdi register, i=0,1,3,4) .................................................................... .... 137 15.1.2 port pi register (pi register, i=0 to 4) ................................................................................ ............. 137 15.1.3 pull-up control register 0, pull-up control register 1 (pur0 and pur1 registers) ................. 137 15.1.4 port p1 drive capacity control register (drr register) .............................................................. 137 15.2 port setting .............................................................................................................. .. 145 15.3 unassigned pin handling ........................................................................................ 151 chapter 16. electrical characteristics ............................. 152 chapter 17. flash memory version ................................. 164
a-4 17.1 overview .................................................................................................................. .. 164 17.2 memory map .............................................................................................................. 16 5 17.3 functions to prevent flash memory from rewriting............................................ 166 17.3.1 id code check function .................................................................................................. ................ 166 17.4 cpu rewrite mode .................................................................................................... 167 17.4.1 ew0 mode ................................................................................................................ .......................... 168 17.4.2 ew1 mode ................................................................................................................ .......................... 168 17.4.3 software commands ....................................................................................................... ................. 174 17.4.4 status register ......................................................................................................... ......................... 178 17.4.5 full status check ....................................................................................................... ....................... 179 17.5 standard serial i/o mode ......................................................................................... 181 17.5.1 id code check function .................................................................................................. ................ 181 chapter 18. on-chip debugger ........................................ 185 18.1 address match interrupt .......................................................................................... 185 18.2 single step interrupt ................................................................................................ 185 18.3 uart1 ..................................................................................................................... ... 185 18.4 brk instruction ........................................................................................................ 188 chapter 19. usage notes .................................................. 186 19.1 stop mode and wait mode ....................................................................................... 186 19.1.1 stop mode ............................................................................................................... ........................... 186 19.1.2 wait mode ............................................................................................................... ........................... 186 19.2 interrupts ................................................................................................................ ... 187 19.2.1 reading address 00000 16 ............................................................................................................................. ............... 187 19.2.2 sp setting .............................................................................................................. ............................ 187 19.2.3 external interrupt and key input interrupt .............................................................................. ....... 187 19.2.4 watchdog timer interrupt ................................................................................................ ................ 187 19.2.5 changing interrupt factor ............................................................................................... ................. 188 19.2.6 changing interrupt control register ..................................................................................... ......... 189 19.3 clock generation circuit ......................................................................................... 190 19.3.1 oscillation stop detection function ..................................................................................... .......... 190 19.3.2 oscillation circuit constants ........................................................................................... ................ 190 19.4 timers .................................................................................................................... .... 191 19.3.1 timers x, y and z ....................................................................................................... ....................... 191 19.3.2 timer x ................................................................................................................. ................................ 19 19.3.3 timer y ................................................................................................................. .............................. 191 19.3.4 timer z ................................................................................................................. .............................. 191 19.3.5 timer c ................................................................................................................. .............................. 191 19.5 serial interface .......................................................................................................... 192 19.6 a/d converter............................................................................................................ 1 93 19.7 flash memory version ............................................................................................. 194 19.7.1 cpu rewrite mode ........................................................................................................ .................... 194 19.8 noise ..................................................................................................................... ..... 197 chapter 20. usage notes for on-chip debugger ............ 198
a-5 appendix 1 package dimensions .................................... 199 appendix 2 connecting examples for serial writer and on-chip debugging emulator .......................................... 200 appendix 3 example of oscillation evaluation circuit .. 202 register index ................................................................... 203
b-1 sfr page reference w a t c h d o g t i m e r s t a r t r e g i s t e rw d t s6 9 w a t c h d o g t i m e r c o n t r o l r e g i s t e rw d c6 9 p r o c e s s o r m o d e r e g i s t e r 0p m 04 5 s y s t e m c l o c k c o n t r o l r e g i s t e r 0c m 03 1 s y s t e m c l o c k c o n t r o l r e g i s t e r 1c m 13 1 a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e ra i e r6 7 p r o t e c t r e g i s t e rp r c r4 4 p r o c e s s o r m o d e r e g i s t e r 1p m 14 5 o s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e ro c d3 2 i n t 0 i n p u t f i l t e r s e l e c t r e g i s t e ri n t 0 f6 0 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 a d d r e s s r e g i s t e rs y m b o l a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0r m a d 06 7 a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1r m a d 16 7 w a t c h d o g t i m e r r e s e t r e g i s t e rw d t r6 9 p a g e h i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0 h r 0 3 3 h i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1 h r 1 3 3 v o l t a g e d e t e c t i o n r e g i s t e r 1v c r 12 2 v o l t a g e d e t e c t i o n r e g i s t e r 2v c r 22 2 v o l t a g e d e t e c t i o n i n t e r r u p t r e g i s t e rd 4 i n t2 3 a d d r e s s r e g i s t e rs y m b o l p a g e u a r t 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r s 0 t i c5 3 u a r t 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r s 0 r i c5 3 u a r t 1 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r s 1 t i c5 3 u a r t 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r s 1 r i c5 3 k e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rk u p i c5 3 a d c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e ra d i c5 3 i n t 1 i n t e r r u p t c o n t r o l r e g i s t e ri n t 1 i c5 3 i n t 2 i n t e r r u p t c o n t r o l r e g i s t e ri n t 2 i c5 3 i n t 0 i n t e r r u p t c o n t r o l r e g i s t e ri n t 0 i c5 3 i n t 3 i n t e r r u p t c o n t r o l r e g i s t e ri n t 3 i c5 3 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 0 0 5 4 1 6 0 0 5 5 1 6 0 0 5 6 1 6 0 0 5 7 1 6 0 0 5 8 1 6 0 0 5 9 1 6 0 0 5 a 1 6 0 0 5 b 1 6 0 0 5 c 1 6 0 0 5 d 1 6 0 0 5 e 1 6 0 0 5 f 1 6 0 0 6 0 1 6 0 0 6 1 1 6 0 0 6 2 1 6 0 0 6 3 1 6 0 0 6 4 1 6 0 0 6 5 1 6 0 0 6 6 1 6 0 0 6 7 1 6 0 0 6 8 1 6 0 0 6 9 1 6 0 0 6 a 1 6 0 0 6 b 1 6 0 0 6 c 1 6 0 0 6 d 1 6 0 0 6 e 1 6 0 0 6 f 1 6 0 0 7 0 1 6 0 0 7 1 1 6 0 0 7 2 1 6 0 0 7 3 1 6 0 0 7 4 1 6 0 0 7 5 1 6 0 0 7 6 1 6 0 0 7 7 1 6 0 0 7 8 1 6 0 0 7 9 1 6 0 0 7 a 1 6 0 0 7 b 1 6 0 0 7 c 1 6 0 0 7 d 1 6 0 0 7 e 1 6 0 0 7 f 1 6 t i m e r x i n t e r r u p t c o n t r o l r e g i s t e rt x i c5 3 t i m e r y i n t e r r u p t c o n t r o l r e g i s t e rt y i c5 3 t i m e r z i n t e r r u p t c o n t r o l r e g i s t e rt z i c5 3 t i m e r c i n t e r r u p t c o n t r o l r e g i s t e rt c i c5 3 c o m p a r e 1 i n t e r r u p t c o n t r o l r e g i s t e r c m p 1 i c5 3 c o m p a r e 0 i n t e r r u p t c o n t r o l r e g i s t e r c m p 0 i c5 3 blank columns are all reserved space. no use is allowed.
b-2 sfr page reference a d d r e s s r e g i s t e rs y m b o l p a g e 0 0 8 0 1 6 0 0 8 1 1 6 0 0 8 2 1 6 0 0 8 3 1 6 0 0 8 4 1 6 0 0 8 5 1 6 0 0 8 6 1 6 0 0 8 7 1 6 0 0 8 8 1 6 0 0 8 9 1 6 0 0 8 a 1 6 0 0 8 b 1 6 0 0 8 c 1 6 0 0 8 d 1 6 0 0 8 e 1 6 0 0 8 f 1 6 0 0 9 0 1 6 0 0 9 1 1 6 0 0 9 2 1 6 0 0 9 3 1 6 0 0 9 4 1 6 0 0 9 5 1 6 0 0 9 6 1 6 0 0 9 7 1 6 0 0 9 8 1 6 0 0 9 9 1 6 0 0 9 a 1 6 0 0 9 b 1 6 0 0 9 c 1 6 0 0 9 d 1 6 0 0 9 e 1 6 0 0 9 f 1 6 0 0 a 0 1 6 0 0 a 1 1 6 0 0 a 2 1 6 0 0 a 3 1 6 0 0 a 4 1 6 0 0 a 5 1 6 0 0 a 6 1 6 0 0 a 7 1 6 0 0 a 8 1 6 0 0 a 9 1 6 0 0 a a 1 6 0 0 a b 1 6 0 0 a c 1 6 0 0 a d 1 6 0 0 a e 1 6 0 0 a f 1 6 0 0 b 0 1 6 0 0 b 1 1 6 0 0 b 2 1 6 0 0 b 3 1 6 0 0 b 4 1 6 0 0 b 5 1 6 0 0 b 6 1 6 0 0 b 7 1 6 0 0 b 8 1 6 0 0 b 9 1 6 0 0 b a 1 6 0 0 b b 1 6 0 0 b c 1 6 0 0 b d 1 6 0 0 b e 1 6 0 0 b f 1 6 t i m e r x r e g i s t e rt x7 2 t i m e r y s e c o n d a r yt y s c8 1 e x t e r n a l i n p u t e n a b l e r e g i s t e ri n t e n6 0 pr e s c a l e r yp r e y8 1 u a r t 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r u 0 m r1 1 2 u a r t 0 r e c e i v e b u f f e r r e g i s t e r u 0 r b1 1 1 u a r t 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r u 1 m r1 1 2 u a r t 1 t r a n s m i t b u f f e r r e g i s t e ru 1 t b1 1 1 u a r t 1 r e c e i v e b u f f e r r e g i s t e r u 1 r b1 1 1 u a r t 0 b i t r a t e r e g i s t e ru 0 b r g1 1 1 u a r t 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 u 0 c 01 1 2 u a r t 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 u 0 c 11 1 3 u a r t 1 b i t r a t e r e g i s t e ru 1 b r g1 1 1 u a r t 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 u 1 c 01 1 2 u a r t 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 u 1 c 11 1 3 t i m e r y , z m o d e r e g i s t e rt y z m r8 0 / 8 8 t i m e r y p r i m a r yt y p r8 1 t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r p u m8 2 / 9 0 pr e s c a l e r zp r e z8 9 t i m e r z s e c o n d a r yt z s c8 9 t i m e r z p r i m a r yt z p r8 9 t i m e r y , z o u t p u t c o n t r o l r e g i s t e rt y z o c8 1 / 8 9 t i m e r x m o d e r e g i s t e rt x m r7 1 pr e s c a l e r xp r e x7 2 t i m e r c o u n t s o u r c e s e t t i n g r e g i s t e rt c s s 7 2 / 8 2 / 9 0 t i m e r c r e g i s t e rt c1 0 3 k e y i n p u t e n a b l e r e g i s t e rk i e n6 5 t i m e r c c o n t r o l r e g i s t e r 0t c c 01 0 3 t i m e r c c o n t r o l r e g i s t e r 1t c c 11 0 4 u a r t t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2 u c o n1 1 3 u a r t 0 t r a n s m i t b u f f e r r e g i s t e ru 0 t b1 1 1 c a p t u r e a n d c o m p a r e 0 r e g i s t e rt m 01 0 3 c o m p a r e 1 r e g i s t e rt m 11 0 3 a d d r e s s register symbol p a g e 0 0 c 0 1 6 0 0 c 1 1 6 0 0 c 2 1 6 0 0 c 3 1 6 0 0 c 4 1 6 0 0 c 5 1 6 0 0 c 6 1 6 0 0 c 7 1 6 0 0 c 8 1 6 0 0 c 9 1 6 0 0 c a 1 6 0 0 c b 1 6 0 0 c c 1 6 0 0 c d 1 6 0 0 c e 1 6 0 0 c f 1 6 0 0 d 0 1 6 0 0 d 1 1 6 0 0 d 2 1 6 0 0 d 3 1 6 0 0 d 4 1 6 0 0 d 5 1 6 0 0 d 6 1 6 0 0 d 7 1 6 0 0 d 8 1 6 0 0 d 9 1 6 0 0 d a 1 6 0 0 d b 1 6 0 0 d c 1 6 0 0 d d 1 6 0 0 d e 1 6 0 0 d f 1 6 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 03fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 a d r e g i s t e ra d1 2 7 ad control register 0 adcon0 126 a d c o n t r o l r e g i s t e r 2a d c o n 21 2 7 a d c o n t r o l r e g i s t e r 1 a d c o n 11 2 6 port p0 register p0 143 port p0 direction register pd0 143 p o r t p 1 r e g i s t e rp 11 4 3 port p1 direction register pd1 143 port p3 register p3 143 p o r t p 3 d i r e c t i o n r e g i s t e rp d 31 4 3 p o r t p 4 r e g i s t e rp 41 4 3 port p4 direction register pd4 143 p u l l - u p c o n t r o l r e g i s t e r 0 p u r 01 4 4 p o r t p 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r d r r1 4 4 pull-up control register 1 pur1 144 f l a s h m e m o r y c o n t r o l r e g i s t e r 1 f m r 11 7 1 f l a s h m e m o r y c o n t r o l r e g i s t e r 0 f m r 01 7 0 f l a s h m e m o r y c o n t r o l r e g i s t e r 4 f m r 41 7 1 t i m e r c o u t p u t c o n t r o l r e g i s t e r t c o u t1 0 6 blank columns are all reserved space. no use is allowed.
r8c/11 group single-chip 16-bit cmos microcomputer rev.1.20 jan 27, 2006 page 1 of 204 rej09b0062-0120 rej09b0062-0120 rev.1.20 jan 27, 2006 1. overview this mcu is built using the high-performance silicon gate cmos process using a r8c/tiny series cpu core and is packaged in a 32-pin plastic molded lqfp. this mcu operates using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, it is capable of executing instructions at high speed. 1.1 applications electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
rev.1.20 jan 27, 2006 page 2 of 204 rej09b0062-0120 r8c/11 group 1. overview table 1.1 performance outline 1.2 performance overview table 1.1. lists the performance outline of this mcu. item performance cpu number of basic instructions 89 instructions minimum instruction execution time 50 ns (f(x in ) = 20 mh z , v cc = 3.0 to 5.5 v) 100 ns (f(x in ) = 10 mh z , v cc = 2.7 to 5.5 v) operating mode single-chip address space 1m bytes memory capacity see table 1.2. peripheral port input/output: 22 (including led drive port), input: 2 function led drive port i/o port: 8 timer timer x: 8 bits x 1 channel, timer y: 8 bits x 1 channel, timer z: 8 bits x 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits x 1 channel (circuits of input capture and output compare) serial interface ? channel clock synchronous, uart ? channel uart a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits x 1 (with prescaler) interrupt internal: 11 factors, external: 5 factors, software: 4 factors, priority level: 7 levels clock generation circuit 2 circuits ?ain clock generation circuit (equipped with a built-in feedback resistor) ?n-chip oscillator (high speed, low speed) on high-speed on-chip oscillator the frequency adjust- ment function is usable. oscillation stop detection function main clock oscillation stop detection function voltage detection circuit included power on reset circuit included electrical supply voltage v cc = 3.0 to 5.5 v (f(x in ) = 20 mh z ) characteristics v cc = 2.7 to 5.5 v (f(x in ) = 10 mh z ) power consumption typ. 9 ma (v cc = 5.0 v, (f(x in ) = 20 mh z ) typ. 5 ma (v cc = 3.0 v, (f(x in ) = 10 mh z ) typ. 35 a (v cc = 3.0 v, wait mode, peripheral clock off) typ. 0.7 a (v cc = 3.0 v, stop mode) flash memory program/erase supply voltage v cc = 2.7 to 5.5 v program/erase endurance 100 times operating ambient temperature -20 to 85 ? -40 to 85 ? (d-version) package 32-pin plastic mold lqfp
rev.1.20 jan 27, 2006 page 3 of 204 rej09b0062-0120 r8c/11 group 1. overview 1.3 block diagram figure 1.1 shows this mcu block diagram. figure 1.1 block diagram t i m e r x ( 8 b i t s ) t i m e r y ( 8 b i t s ) t i m e r z ( 8 b i t s ) t i m e r c ( 1 6 b i t s ) w a t c h d o g t i m e r ( 1 5 b i t s ) m e m o r y r 8 c / t i n y s e r i e s c p u c o r e i / o p o r t p o r t p 0 8 port p1 8 p o r t p 3 5 m u l t i p l i e r system clock generator x i n - x o u t h i g h - s p e e d o n - c h i p o s c i l l a t o r l o w - s p e e d o n - c h i p o s c i l l a t o r u a r t ( 8 b i t s ? ? ?
rev.1.20 jan 27, 2006 page 4 of 204 rej09b0062-0120 r8c/11 group 1. overview 1.4 product information table 1.2 lists the product information. table 1.2 product information ram capacity rom capacity package type remarks type no. as of january 2006 flash memory version r5f21112fp plqp0032gb-a 8k bytes 512 bytes plqp0032gb-a 12k bytes 768 bytes plqp0032gb-a 16k bytes 1k bytes r5f21113fp r5f21114fp r5f21112dfp plqp0032gb-a 8k bytes 512 bytes plqp0032gb-a 12k bytes 768 bytes plqp0032gb-a 16k bytes 1k bytes R5F21113DFP r5f21114dfp d version figure 1.2 type no., memory size, and package package type: fp : plqp0032gb-a rom capacity: 2 : 8 kbytes. 3 : 12 kbytes. 4 : 16 kbytes. memory type: f: flash memory version type no. r 5 f 21 11 4 d fp r8c/11 group r8c/tiny series classification: d: operating ambient temperature 40 c to 85 c no symbol: operating ambient temperature 20 c to 85 c renesas mcu renesas semiconductors
rev.1.20 jan 27, 2006 page 5 of 204 rej09b0062-0120 r8c/11 group 1. overview package: plqp0032gb-a (32p6u-a) figure 1.3 pin assignments (top view) pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r8c/11 group x i n / p 4 6 v s s r e s e t v c c c n v s s p 1 7 / i n t 1 / c n t r 0 p1 6 /clk 0 p1 5 /rxd 0 p1 4 /txd 0 p 3 7 / t x d 1 0 / r x d 1 p 3 0 / c n t r 0 / c m p 1 0 p 3 3 / i n t 3 / p 3 1 / t z o u t / c m p 1 1 p 3 2 / i n t 2 / c n t r 1 / c m p 1 2 i v c c a v s s a v c c / v r e f p0 3 /an 4 p0 2 /an 5 p0 1 /an 6 p 0 0 / a n 7 /t x d 1 1 p 0 6 / a n 1 p0 5 /an 2 p 0 4 / a n 3 p4 5 /int 0 p1 0 /ki 0 /an 8 /cmp0 0 p1 1 /ki 1 /an 9 /cmp0 1 p1 2 /ki 2 /an 10 /cmp0 2 p1 3 /ki 3 /an 11 p 0 7 / a n 0 mode t c i n n o t e s : 1 . p 4 7 f u n c t i o n s o n l y a s a n i n p u t p o r t . 2. w h e n u s i n g o n - c h i p d e b u g g e r , d o n o t u s e p i n s p 0 0 / a n 7 / t x d 1 1 a n d p 3 7 / t x d 1 0 / r x d 1 . 3 . d o n o t c o n n e c t i v c c t o v c c . x o u t / p 4 7 ( 1 ) 1.5 pin assignments figure 1.3 shows the pin configuration (top view).
rev.1.20 jan 27, 2006 page 6 of 204 rej09b0062-0120 r8c/11 group 1. overview signal name pin name i/o type power supply vcc, i input vss ivcc ivcc o analog power avcc, avss i supply input reset input ___________ reset i cnvss cnvss i mode mode i main clock input x in i main clock output x out o _____ int interrupt input _______ _______ int 0 to int 3 i key input interrupt _____ _____ ki 0 to ki 3 i timer x cntr 0 i/o ____________ cntr 0 o timer y cntr 1 i/o timer z tz out o timer c tc in i cmp0 0 to cmp0 2 , o cmp1 0 to cmp1 2 serial interface clk 0 i/o rxd 0 , rxd 1 i txd 0 , txd 10 ,o txd 11 reference voltage v ref i input a/d converter an 0 to an 11 i i/o port p0 0 to p0 7 , i/o p1 0 to p1 7 , p3 0 to p3 3 , p3 7 , p4 5 input port p4 6 , p4 7 i function apply 2.7 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. this pin is to stabilize internal power supply. connect this pin to vss via a capacitor (0.1 l on this pin resets the mcu. connect this pin to vss via a resistor. (1) connect this pin to vcc via a resistor. these pins are provided for the main clock generat- ing circuit i/o. connect a ceramic resonator or a crys- tal oscillator between the x in and x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. ______ int interrupt input pins. key input interrupt pins. timer x i/o pin timer x output pin timer y i/o pin timer z output pin timer c input pin timer c output pins transfer clock i/o pin. serial data input pins. serial data output pins. reference voltage input pin for a/d converter. con- nect the v ref pin to vcc. analog input pins for a/d converter these are 8-bit cmos i/o ports. each port has an i/o select direction register, allowing each pin in that port to be directed for input or output individually. any port set to input can select whether to use a pull- up resistor or not by program. p1 0 to p1 7 also function as led drive ports. port for input-only 1.6 pin description table 1.3 shows the pin description table 1.3 pin description notes : 1. refer to "19.8 noise" for the connecting reference resistor value.
r8c/11 group 2. central processing unit (cpu) rev.1.20 jan 27, 2006 page 7 of 204 rej09b0062-0120 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. two sets of register banks are provided. 2.1 data registers (r0, r1, r2 and r3) r0 is a 16-bit register for transfer, arithmetic and logic operations. the same applies to r1 to r3. the r0 can be split into high-order bit (r0h) and low-order bit (r0l) to be used separately as 8-bit data registers. the same applies to r1h and r1l as r0h and r0l. r2 can be combined with r0 to be used as a 32-bit data register (r2r0). the same applies to r3r1 as r2r0. d a t a r e g i s t e r s ( 1 ) a d d r e s s r e g i s t e r s ( 1 ) f r a m e b a s e r e g i s t e r s ( 1 ) p r o g r a m c o u n t e r i n t e r r u p t t a b l e r e g i s t e r u s e r s t a c k p o i n t e r interrupt stack pointer static base register flag register n o t e s : 1 . a r e g i s t e r b a n k c o m p r i s e s t h e s e r e g i s t e r s . t w o s e t s o f r e g i s t e r b a n k s a r e p r o v i d e d r0h (high-order of r0) b 1 5 b 8 b7 b 0 r 3 i n t b h u s p isp sb c d z s b o i u i p l r0l (low-order of r0) r1h (high-order of r1) r1l (low-order of r1) r 2 b 3 1 r3 r2 a1 a0 f b b 1 9 i n t b l b 1 5 b 0 pc b19 b 0 b 1 5 b 0 f l g b15 b0 b 1 5 b 0 b7 b 8 reserved bit carry flag d e b u g f l a g z e r o f l a g sign flag register bank select flag o v e r f l o w f l a g i n t e r r u p t e n a b l e f l a g s t a c k p o i n t e r s e l e c t f l a g r e s e r v e d b i t processor interrupt priority level t h e 4 - h i g h o r d e r b i t s o f i n t b a r e i n t b h a n d t h e 1 6 - l o w b i t s o f i n t b a r e i n t b l . figure 2.1 cpu register
r8c/11 group 2. central processing unit (cpu) rev.1.20 jan 27, 2006 page 8 of 204 rej09b0062-0120 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addressing and address register relative addressing. they also are used for transfer, arithmetic and logic operations. the same applies to a1 as a0. a0 can be combined with a0 to be used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc, 20 bits wide, indicates the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointer (sp), usp and isp, are 16 bits wide each. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is a 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit. 2.8.2 debug flag (d) the d flag is for debug only. set to 0 . 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0 . 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0 . 2.8.5 register bank select flag (b) the register bank 0 is selected when the b flag is 0 . the register bank 1 is selected when this flag is set to 1 . 2.8.6 overflow flag (o) the o flag is set to 1 when the operation resulted in an overflow; otherwise, 0 . 2.8.7 interrupt enable flag (i) the i flag enables a maskable interrupt. an interrupt is disabled when the i flag is set to 0 , and are enabled when the i flag is set to 1 . the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0 , usp is selected when the u flag is set to 1 . the u flag is set to 0 when a hardware interrupt request is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. if a requested interrupt has greater priority than ipl, the interrupt is enabled. 2.8.10 reserved bit when write to this bit, set to 0 . when read, its content is indeterminate.
r8c/11 group 3. memory rev.1.20 jan 27, 2006 page 9 of 204 rej09b0062-0120 3. memory figure 3.1 is a memory map of this mcu. this mcu provides 1-mbyte address space from addresses 00000 16 to fffff 16 . the internal rom is allocated lower addresses beginning with address 0ffff 16 . for example, a 16-kbyte internal rom is allocated addresses from 0c000 16 to 0ffff 16 . the fixed interrupt vector table is allocated addresses 0ffdc 16 to 0ffff 16 . they store the starting address of each interrupt routine. the internal ram is allocated higher addresses beginning with address 00400 16 . for example, a 1-kbyte internal ram is allocated addresses 00400 16 to 007ff 16 . the internal ram is used not only for storing data, but for calling subroutines and stacks when interrupt request is acknowledged. special function registers (sfr) are allocated addresses 00000 16 to 002ff 16 . the peripheral function control registers are located them. all addresses, which have nothing allocated within the sfr, are re- served area and cannot be accessed by users. figure 3.1 memory map 00000 16 0yyyy 16 0ffff 16 002ff 16 00400 16 internal rom sfr (see chapter 4 for details.) 0ffdc 16 0ffff 16 undefined instruction overflow brk instruction address match single step watchdog timer,oscillation stop detection,voltage detection reset (reserved) type name 0xxxx 16 internal ram fffff 16 address 0xxxx 16 005ff 16 internal ram size 007ff 16 512 bytes 1k bytes 006ff 16 768 bytes address 0yyyy 16 0e000 16 internal rom size 0c000 16 8k bytes 16k bytes 0d000 16 12k bytes expansion area (reserved) r5f21114fp, r5f21114dfp r5f21113fp, R5F21113DFP r5f21112fp, r5f21112dfp notes : 1. blank spaces are reserved. no access is allowed.
r8c/11 group 4. special function register (sfr) rev.1.20 jan 27, 2006 page 10 of 204 rej09b0062-0120 watchdog timer start register wdts xx 16 w a t c h d o g t i m e r c o n t r o l r e g i s t e rw d c0 0 0 1 1 1 1 1 2 p r o c e s s o r m o d e r e g i s t e r 0p m 00 0 1 6 s y s t e m c l o c k c o n t r o l r e g i s t e r 0c m 00 1 1 0 1 0 0 0 2 s y s t e m c l o c k c o n t r o l r e g i s t e r 1c m 10 0 1 0 0 0 0 0 2 a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e ra i e rx x x x x x 0 0 2 p r o t e c t r e g i s t e rp r c r0 0 x x x 0 0 0 2 p r o c e s s o r m o d e r e g i s t e r 1p m 10 0 1 6 1 . b l a n k s p a c e s a r e r e s e r v e d . n o a c c e s s i s a l l o w e d . 2 . s o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r . 3 . o w i n g t o r e s e t i n p u t . 4 . i n t h e c a s e o f r e s e t p i n = h r e t a i n i n g . o s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e ro c d0 0 0 0 0 1 0 0 2 int0 input filter select register int0f xxxxx000 2 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 address r e g i s t e r symbol after reset address match interrupt register 0 rmad0 00 16 00 16 x0 16 a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1r m a d 10 0 1 6 0 0 1 6 x 0 1 6 w a t c h d o g t i m e r r e s e t r e g i s t e rw d t rx x 1 6 h i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0h r 00 0 1 6 h i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 1h r 14 0 1 6 voltage detection register 1 vcr1 00001000 2 v o l t a g e d e t e c t i o n r e g i s t e r 2v c r 20 0 1 6 1 0 0 0 0 0 0 0 2 voltage detection interrupt register d4int 00 16 x : u n d e f i n e d n o t e s : ( 2 ) 01000001 2 ( 4 ) ( 3 ) ( 2 ) ( 2 ) ( 4 ) ( 3 ) 4. special function register (sfr) sfr(special function register) is the control register of peripheral functions. tables 4.1 to 4.4 list the sfr information table 4.1 sfr information(1) (1)
r8c/11 group 4. special function register (sfr) rev.1.20 jan 27, 2006 page 11 of 204 rej09b0062-0120 u a r t 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r s 0 t i cx x x x x 0 0 0 2 u a r t 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r s 0 r i cx x x x x 0 0 0 2 uart1 transmit interrupt control register s1tic xxxxx000 2 u a r t 1 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r s 1 r i cx x x x x 0 0 0 2 k e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e rk u p i cx x x x x 0 0 0 2 a d c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e ra d i cx x x x x 0 0 0 2 int1 interrupt control register int1ic xxxxx000 2 int2 interrupt control register int2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int3 interrupt control register int3ic xxxxx000 2 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 0 0 5 4 1 6 0 0 5 5 1 6 0 0 5 6 1 6 0 0 5 7 1 6 0 0 5 8 1 6 0 0 5 9 1 6 0 0 5 a 1 6 0 0 5 b 1 6 0 0 5 c 1 6 0 0 5 d 1 6 0 0 5 e 1 6 0 0 5 f 1 6 0 0 6 0 1 6 0 0 6 1 1 6 0 0 6 2 1 6 0 0 6 3 1 6 0 0 6 4 1 6 0 0 6 5 1 6 0 0 6 6 1 6 0 0 6 7 1 6 0 0 6 8 1 6 0 0 6 9 1 6 0 0 6 a 1 6 0 0 6 b 1 6 0 0 6 c 1 6 0 0 6 d 1 6 0 0 6 e 1 6 0 0 6 f 1 6 0 0 7 0 1 6 0 0 7 1 1 6 0 0 7 2 1 6 0 0 7 3 1 6 0 0 7 4 1 6 0 0 7 5 1 6 0 0 7 6 1 6 0 0 7 7 1 6 0 0 7 8 1 6 0 0 7 9 1 6 0 0 7 a 1 6 0 0 7 b 1 6 0 0 7 c 1 6 0 0 7 d 1 6 0 0 7 e 1 6 0 0 7 f 1 6 a d d r e s s r e g i s t e r symbol a f t e r r e s e t timer x interrupt control register txic xxxxx000 2 timer y interrupt control register tyic xxxxx000 2 t i m e r z i n t e r r u p t c o n t r o l r e g i s t e rt z i cx x x x x 0 0 0 2 t i m e r c i n t e r r u p t c o n t r o l r e g i s t e rt c i cx x x x x 0 0 0 2 c o m p a r e 1 i n t e r r u p t c o n t r o l r e g i s t e r c m p 1 i cx x x x x 0 0 0 2 c o m p a r e 0 i n t e r r u p t c o n t r o l r e g i s t e r c m p 0 i cx x x x x 0 0 0 2 x : u n d e f i n e d n o t e s : 1 . b l a n k s p a c e s a r e r e s e r v e d . n o a c c e s s i s a l l o w e d . table 4.2 sfr information(2) (1)
r8c/11 group 4. special function register (sfr) rev.1.20 jan 27, 2006 page 12 of 204 rej09b0062-0120 0 0 8 0 1 6 0 0 8 1 1 6 0 0 8 2 1 6 0 0 8 3 1 6 0 0 8 4 1 6 0 0 8 5 1 6 0 0 8 6 1 6 0 0 8 7 1 6 0 0 8 8 1 6 0 0 8 9 1 6 0 0 8 a 1 6 0 0 8 b 1 6 0 0 8 c 1 6 0 0 8 d 1 6 0 0 8 e 1 6 0 0 8 f 1 6 0 0 9 0 1 6 0 0 9 1 1 6 0 0 9 2 1 6 0 0 9 3 1 6 0 0 9 4 1 6 0 0 9 5 1 6 0 0 9 6 1 6 0 0 9 7 1 6 0 0 9 8 1 6 0 0 9 9 1 6 0 0 9 a 1 6 0 0 9 b 1 6 0 0 9 c 1 6 0 0 9 d 1 6 0 0 9 e 1 6 0 0 9 f 1 6 0 0 a 0 1 6 0 0 a 1 1 6 0 0 a 2 1 6 0 0 a 3 1 6 0 0 a 4 1 6 0 0 a 5 1 6 0 0 a 6 1 6 0 0 a 7 1 6 0 0 a 8 1 6 0 0 a 9 1 6 0 0 a a 1 6 0 0 a b 1 6 0 0 a c 1 6 0 0 a d 1 6 0 0 a e 1 6 0 0 a f 1 6 0 0 b 0 1 6 0 0 b 1 1 6 0 0 b 2 1 6 0 0 b 3 1 6 0 0 b 4 1 6 0 0 b 5 1 6 0 0 b 6 1 6 0 0 b 7 1 6 0 0 b 8 1 6 0 0 b 9 1 6 0 0 b a 1 6 0 0 b b 1 6 0 0 b c 1 6 0 0 b d 1 6 0 0 b e 1 6 0 0 b f 1 6 t i m e r x r e g i s t e rt xf f 1 6 t i m e r y s e c o n d a r y r e g i s t e rt y s cf f 1 6 e x t e r n a l i n p u t e n a b l e r e g i s t e ri n t e n0 0 1 6 p r e s c a l e r y r e g i s t e rp r e yf f 1 6 u a r t 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r u 0 m r0 0 1 6 uart0 transmit buffer register u0tb xx 16 xx 16 u a r t 0 r e c e i v e b u f f e r r e g i s t e r u 0 r bx x 1 6 x x 1 6 u a r t 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r u 1 m r0 0 1 6 u a r t 1 t r a n s m i t b u f f e r r e g i s t e ru 1 t bx x 1 6 x x 1 6 u a r t 1 r e c e i v e b u f f e r r e g i s t e r u 1 r bx x 1 6 x x 1 6 uart0 bit rate register u0brg xx 16 uart0 transmit/receive control register 0 u0c0 00001000 2 u a r t 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 u 0 c 10 0 0 0 0 0 1 0 2 u a r t 1 b i t r a t e r e g i s t e ru 1 b r gx x 1 6 u a r t 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 u 1 c 00 0 0 0 1 0 0 0 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart transmit/receive control register 2 ucon 00 16 a d d r e s s r e g i s t e r symbol a f t e r r e s e t t i m e r y , z m o d e r e g i s t e rt y z m r0 0 1 6 t i m e r y p r i m a r y r e g i s t e rt y p rf f 1 6 t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e rp u m0 0 1 6 p r e s c a l e r z r e g i s t e rp r e zf f 1 6 t i m e r z s e c o n d a r y r e g i s t e rt z s cf f 1 6 t i m e r z p r i m a r y r e g i s t e rt z p rf f 1 6 t i m e r y , z o u t p u t c o n t r o l r e g i s t e rt y z o c0 0 1 6 t i m e r x m o d e r e g i s t e rt x m r0 0 1 6 p r e s c a l e r x r e g i s t e rp r e xf f 1 6 t i m e r c o u n t s o u r c e s e t r e g i s t e rt c s s0 0 1 6 t i m e r c r e g i s t e rt c0 0 1 6 0 0 1 6 k e y i n p u t e n a b l e r e g i s t e rk i e n0 0 1 6 timer c control register 0 tcc0 00 16 timer c control register 1 tcc1 00 16 c a p t u r e , c o m p a r e 0 r e g i s t e rt m 00 0 1 6 0 0 1 6 compare 1 register tm1 ff 16 ff 16 x : u n d e f i n e d n o t e s : 1 . b l a n k s p a c e s a r e r e s e r v e d . n o a c c e s s i s a l l o w e d . 2 . w h e n o u t p u t c o m p a r e m o d e ( t h e t c c 1 3 b i t i n t h e t c c 1 r e g i s t e r = 1 ) i s s e l e c t e d , t h e v a l u e a f t e r r e s e t i s s e t t o f f f f 1 6 . ( 2 ) table 4.3 sfr information(3) (1)
r8c/11 group 4. special function register (sfr) rev.1.20 jan 27, 2006 page 13 of 204 rej09b0062-0120 0 0 c 0 1 6 0 0 c 1 1 6 0 0 c 2 1 6 0 0 c 3 1 6 0 0 c 4 1 6 0 0 c 5 1 6 0 0 c 6 1 6 0 0 c 7 1 6 0 0 c 8 1 6 0 0 c 9 1 6 0 0 c a 1 6 0 0 c b 1 6 0 0 c c 1 6 0 0 c d 1 6 0 0 c e 1 6 0 0 c f 1 6 0 0 d 0 1 6 0 0 d 1 1 6 0 0 d 2 1 6 0 0 d 3 1 6 0 0 d 4 1 6 0 0 d 5 1 6 0 0 d 6 1 6 0 0 d 7 1 6 0 0 d 8 1 6 0 0 d 9 1 6 0 0 d a 1 6 0 0 d b 1 6 0 0 d c 1 6 0 0 d d 1 6 0 0 d e 1 6 0 0 d f 1 6 0 0 e 0 1 6 0 0 e 1 1 6 0 0 e 2 1 6 0 0 e 3 1 6 0 0 e 4 1 6 0 0 e 5 1 6 0 0 e 6 1 6 0 0 e 7 1 6 0 0 e 8 1 6 0 0 e 9 1 6 0 0 e a 1 6 0 0 e b 1 6 0 0 e c 1 6 0 0 e d 1 6 0 0 e e 1 6 0 0 e f 1 6 0 0 f 0 1 6 0 0 f 1 1 6 0 0 f 2 1 6 0 0 f 3 1 6 0 0 f 4 1 6 0 0 f 5 1 6 0 0 f 6 1 6 0 0 f 7 1 6 0 0 f 8 1 6 0 0 f 9 1 6 0 3 f a 1 6 0 0 f b 1 6 0 0 f c 1 6 0 0 f d 1 6 0 0 f e 1 6 0 0 f f 1 6 0 1 b 3 1 6 0 1 b 4 1 6 0 1 b 5 1 6 0 1 b 6 1 6 0 1 b 7 1 6 a d r e g i s t e ra dx x 1 6 x x 1 6 a d c o n t r o l r e g i s t e r 0a d c o n 00 0 0 0 0 x x x 2 a d c o n t r o l r e g i s t e r 2a d c o n 20 0 1 6 a d c o n t r o l r e g i s t e r 1 a d c o n 10 0 1 6 port p0 register p0 xx 16 port p0 direction register pd0 00 16 p o r t p 1 r e g i s t e rp 1x x 1 6 p o r t p 1 d i r e c t i o n r e g i s t e rp d 10 0 1 6 p o r t p 3 r e g i s t e rp 3x x 1 6 p o r t p 3 d i r e c t i o n r e g i s t e rp d 30 0 1 6 p o r t p 4 r e g i s t e rp 4x x 1 6 p o r t p 4 d i r e c t i o n r e g i s t e rp d 40 0 1 6 p u l l - u p c o n t r o l r e g i s t e r 0 p u r 00 0 x x 0 0 0 0 2 p o r t p 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r d r r0 0 1 6 r e g i s t e r symbol after reset a d d r e s s p u l l - u p c o n t r o l r e g i s t e r 1 p u r 1x x x x x x 0 x 2 f l a s h m e m o r y c o n t r o l r e g i s t e r 1 f m r 10 1 0 0 x x 0 x 2 f l a s h m e m o r y c o n t r o l r e g i s t e r 0 f m r 00 0 0 0 0 0 0 1 2 t i m e r c o u t p u t c o n t r o l r e g i s t e r t c o u t0 0 1 6 f l a s h m e m o r y c o n t r o l r e g i s t e r 4 f m r 40 1 0 0 0 0 0 0 2 x : u n d e f i n e d n o t e s : 1 . b l a n k c o l u m n s , 0 1 0 0 1 6 t o 0 1 b 2 1 6 a n d 0 1 b 8 1 6 t o 0 2 f f 1 6 a r e a l l r e s e r v e d . n o a c c e s s i s a l l o w e d . table 4.4 sfr information(4) (1)
r8c/11 group rev.1.20 jan 27, 2006 page 14 of 204 rej09b0062-0120 5. reset there are three types of resets: a hardware reset, a software reset, and an watchdog timer reset. 5.1 hardware reset there are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the cpu. 5.1.1 hardware reset 1 ____________ ____________ a reset is applied using the reset pin. when an l signal is applied to the reset pin while the power supply voltage is within the recommended operating condition, the pins are initial- ____________ ized (see table 5.1 pin status when reset pin level is 'l' ). when the input level at the ____________ reset pin is released from l to h , the cpu and sfr are initialized, and the program is executed starting from the address indicated by the reset vector. figure 5.1 shows the cpu register status after reset and figure 5.2 shows the reset sequence. the internal ram is not ____________ initialized. if the reset pin is pulled l while writing to the internal ram, the internal ram becomes indeterminate. figures 5.3 to 5.4 show the reset circuit example using the hardware reset 1. refer to chapter 4, special function register (sfr) for the status of sfr after reset. when the power supply is stable ____________ (1) apply an l signal to the reset pin. (2) wait for 500 ? (1/f ring-s ? h signal to the reset pin. power on ____________ (1) apply an l signal to the reset pin. (2) let the power supply voltage increase until it meets the recommended operating condi- tion. (3) wait td(p-r) or more until the internal power supply stabilizes. (4) wait for 500 ? (1/f ring-s ? h signal to the reset pin. status pin name p0 p1 p3 0 to p3 3 , p3 7 p4 5 to p4 7 input port input port input port input port ____________ table 5.1 pin status when reset pin level is ? 5.1 hardware reset
r8c/11 group rev.1.20 jan 27, 2006 page 15 of 204 rej09b0062-0120 b15 b0 data register(r0) address register(a0) frame base register(fb) program counter(pc) interrupt table register(intb) user stack pointer(usp) interrupt stack pointer(isp) static base register(sb) flag register(flg) 0000 16 0000 16 0000 16 a a aa aa aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa aa aa a a c d z s b o i u ipl 0000 16 0000 16 0000 16 0000 16 0000 16 b19 b0 content of addresses 0fffe 16 to 0fffc 16 b15 b0 b15 b0 b15 b0 b7 b8 00000 16 data register(r1) data register(r2) data register(r3) address register(a1) 0000 16 0000 16 0000 16 figure 5.1 cpu register status after reset figure 5.2 reset sequence f r i n g - s a d d r e s s ( i n t e r n a l a d d r e s s s i g n a l ) content of reset vector 0 f f f d 1 6 c p u c l o c k c p u c l o c k ? ?
r8c/11 group rev.1.20 jan 27, 2006 page 16 of 204 rej09b0062-0120 figure 5.4 example reset circuit using the hardware reset 1 (voltage check circuit) figure 5.3 example reset circuit using the hardware reset 1 example when v cc = 5v . v cc reset supply voltage detection circuit reset v cc 0v 0v 5v 5v 2.7v more than td(p-r) + 500 s are needed. 5.1 hardware reset r e s e t v c c reset v c c 0 v 0 v m o r e t h a n t d ( p - r ) + 5 0 0 s a r e n e e d e d . equal to or less than 0.2v cc 2 . 7 v
r8c/11 group rev.1.20 jan 27, 2006 page 17 of 204 rej09b0062-0120 this is the reset generated by the voltage detection circuit which is built-in to the microcomputer. the voltage detection circuit monitors the input voltage at vcc input pin. the microcomputer is reset when the voltage at the v cc input pin drops below vdet if all of the following conditions hold true. the vc27 bit in the vcr2 register is set to 1 (voltage detection circuit enabled) the d40 bit in the d4int register is set to 1 (voltage detection interrupt enabled) the d46 bit in the d4int register is set to 1 (hardware reset 2 when going through vdet) when using a digital filter (d41 bit in the d4int register is set to 1 ), set the cm14 bit in the cm1 register to 0 (low-speed on-chip oscillator oscillates). conversely, when the input voltage at the v cc pin rises to vdet or more, the pins, cpu, and sfr are initialized and counting the low-speed on-chip oscillator starts. when counting the low-speed on-chip oscillator clock 32 times, the internal reset is exited and the program is executed beginning with the address indicated by the reset vector. the initialized pins and registers and the status thereof are the same as in hardware reset 1. refer to section 5.4 voltage detection circuit. 5.1.2 hardware reset 2 5.1 hardware reset
r8c/11 group rev.1.20 jan 27, 2006 page 18 of 204 rej09b0062-0120 5.1.3 power-on reset function the power-on reset is the function which can reset the microcomputer without the external reset ____________ circuit. the reset pin should be connected to the v cc pin via about 5 k ? the d40 bit in the d4int register turns to 1 automatically (voltage detection interrupt enabled) the d46 bit in the d4int register turns to 1 automatically (hardware reset 2 when going through vdet) additionally, the hardware reset 2 turns to active after the power-on reset. this is because the vc27 bit in the vcr2 register is set to 1 (voltage detection circuit enabled) after the power-on reset same as the hardware reset 1, so that hardware reset 2 active conditions are all satisfied including above d40 and d46 bit conditions. figure 5.5 shows the power-on reset circuit. figure 5.6 shows the power-on reset operation. figure 5.5 power-on reset circuit internal reset signal reset s r q v cc
r8c/11 group rev.1.20 jan 27, 2006 page 19 of 204 rej09b0062-0120 figure 5.6 power-on reset operation v por1 v cc min v det 3 v det (3) t w(por1) t w(vpor1 vdet) sampling time (1, 2) internal reset signal ( l effective) f ring-s 1 x 32 f ring-s 1 x 32 v por2 notes: 1. hold the voltage of the microcomputer operation voltage range (vccmin or above) within sampling time. 2. a sampling clock is selectable. refer to 5.4 voltage detection circuit for details. 3. v det shows the voltage detection level of the voltage detection circuit. refer to 5.4 voltage detection circuit for details. 4. refer to table 16.6, 16.7 for electrical characteristics. t w(por2) t w(vpor2 vdet) reset vcc about 5 k ?
r8c/11 group rev.1.20 jan 27, 2006 page 20 of 204 rej09b0062-0120 5.2 software reset when the pm03 bit in the pm0 register is set to 1 (microcomputer reset), the microcomputer has its pins, cpu, and sfr initialized. then the program is executed starting from the address indicated by the reset vector. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the cpu. some sfrs are not initialized by the software reset. refer to chapter 4, sfr. 5.3 watchdog timer reset where the pm12 bit in the pm1 register is 1 (reset when watchdog timer underflows), the microcom- puter initializes its pins, cpu and sfr if the watchdog timer underflows. then the program is executed starting from the address indicated by the reset vector. after reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the cpu. some sfrs are not initialized by the watchdog timer reset. refer to chapter 4, sfr. 5.2 software reset, 5.3 watchdog timer reset
r8c/11 group rev.1.20 jan 27, 2006 page 21 of 204 rej09b0062-0120 5.4 voltage detection circuit the voltage detection circuit monitors the input voltage at the v cc pin with respect to vdet. the user program can check for voltage detection using the vc13 bit or set up the voltage detection interrupt register to generate a hardware reset 2 or voltage detection interrupt. figure 5.7 shows the voltage detection circuit. figure 5.8 shows vcr1 and vcr2 registers. figure 5.9 shows the d4int register. figure 5.10 shows an operation example of the voltage detection circuit. fig- ure 5.11 to 5.12 show the operation example of the voltage detection circuit to get out of stop mode. figure 5.7 voltage detection circuit block b3 vcr1 register vc13 bit vc27 v cc internal reference voltage + - noise canceller voltage detection interrupt signal 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 22 of 204 rej09b0062-0120 figure 5.8 vcr1 register and vcr2 register vc13 v o l t a g e d e t e c t i o n r e g i s t e r 1 s y m b o la d d r e s sa f t e r r e s e t (2 ) v c r 10 0 1 9 1 6 0 0 0 0 1 0 0 0 2 v o l t a g e m o n i t o r f l a g (1 ) b i t n a m ef u n c t i o n bit symbol r w b 7b 6b 5b 4b 3b 2b 1b 0 n o t e s : 1 . t h e v c 1 3 b i t i s v a l i d w h e n t h e v c 2 7 b i t i n t h e v c r 2 r e g i s t e r i s s e t t o 1 ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) . t h e v c 1 3 b i t i s s e t t o 1 ( v c c 0 ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) . 2 . s o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r . 0 : v c c < v d e t 1 : v c c 0 should set to 0 v o l t a g e d e t e c t i o n r e g i s t e r 2 s y m b o la d d r e s sa f t e r r e s e t (3 ) v c r 20 0 1 a 1 6 r e s e t i n p u t : 0 0 1 6 r e s e t p i n = h r e t a i n i n g : 1 0 0 0 0 0 0 0 2 b i t n a m e bit symbol b7 b6 b5 b4 b# b2 b1 b0 n o t e s : 1 . s e t t h e p r c 3 b i t i n t h e p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e d ) b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 . s e t t h e v c 2 7 b i t t o 1 ( v o l t a g e d e t e c t c i r c u i t e n a b l e d ) w h e n h a r d w a r e r e s e t 2 i s u s e d . a f t e r t h e v c 2 7 b i t i s s e t t o 1 , t h e v o l t a g e d e t e c t i o n c i r c u i t e l a p s e s f o r t d ( e - a ) b e f o r e s t a r t i n g o p e r a t i o n . 3 . s o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r . vc27 voltage monitor enable bit (2) 0 : v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d 1 : v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d r w r w r w 00000 f u n c t i o n r e s e r v e d b i t should set to 0 ( b 2 - b 0 ) ( b 7 - b 4 ) ( b 6 - b 0 ) 00 ( 1 ) 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 23 of 204 rej09b0062-0120 d 4 0 voltage detection interrupt register (1) symbol address after reset (10) d4int 001f 16 reset input : 00 16 reset pin = "h" retaining : 01000001 2 v o l t a g e d e t e c t i o n i n t e r r u p t e n a b l e b i t (7 ) bit name b i t s y m b o l b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0 0 : disable 1 : enable d 4 1 d 4 2 v o l t a g e c h a n g e d e t e c t i o n f l a g (3 , 4 , 5 ) 0: not detected 1: vdet passing detection d 4 3 w d t o v e r f l o w d e t e c t f l a g (3 , 4 ) 0 : n o t d e t e c t e d ( f l a g c l e a r ) 1 : d e t e c t e d d f 0 s a m p l i n g c l o c k s e l e c t b i t 0 0 : f r i n g- s d i v i d e d b y 1 0 1 : f r i n g - s d i v i d e d b y 2 1 0 : f r i n g - s d i v i d e d b y 4 1 1 : f r i n g - s d i v i d e d b y 8 d f 1 n o t e s : 1 . s e t t h e p r c 3 b i t i n t h e p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 . i f t h e v o l t a g e d e t e c t i o n i n t e r r u p t n e e d s t o b e u s e d t o g e t o u t o f s t o p m o d e a g a i n a f t e r o n c e u s e d f o r t h a t p u r p o s e , r e s e t t h e d 4 1 b i t b y w r i t i n g a 0 a n d t h e n a 1 . 3. v a l i d w h e n t h e v c 2 7 b i t i n t h e v c r 2 r e g i s t e r i s s e t t o 1 ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) . 4 . i f t h e v c 2 7 b i t i s s e t t o 0 ( v o l t a g e d e t e c t i o n c i r c u i t d i s a b l e d ) , t h e d 4 2 a n d d 4 3 b i t s a r e s e t t o 0 ( n o t d e t e c t e d ) . 5 . t h i s b i t i s s e t t o 0 b y w r i t i n g a 0 i n a p r o g r a m . ( w r i t i n g a 1 h a s n o e f f e c t . ) 6 . v a l i d w h e n t h e d 4 0 b i t i s s e t t o 1 ( v o l t a g e d e t e c t i o n i n t e r r u p t e n a b l e d ) . 7 . t h e d 4 0 b i t i s v a l i d w h e n t h e v c 2 7 b i t i n t h e v c r 2 r e g i s t e r i s s e t t o " 1 " ( v o l t a g e d e t e c t i o n c i r c u i t e n a b l e d ) . w h e n s e t t i n g t h e d 4 0 b i t t o " 1 " , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d . ( 1 ) s e t t h e v c 2 7 b i t " 1 " . ( 2 ) w a i t f o r t d ( e - a ) u n t i l t h e d e t e c t e r c i r c u i t o p e r a t e s . ( 3 ) w a i t f o r t h e s a m p l i n g t i m e ( t h e s a m p l i n g c l o c k w h i c h i s s e l e c t e d i n t h e d f 0 b i t t o d f 1 b i t t i m e s 4 c y c l e s . ) ( 4 ) s e t t h e d 4 0 b i t t o " 1 " . ( 5 ) s e t t h e c m 1 4 b i t i n t h e c m 1 r e g i s t e r t o " 0 " ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) . 8 . v a l i d w h e n t h e d 4 1 b i t i s s e t t o " 1 " ( d i g i t a l f i l t e r d i s a b l e d m o d e ) . 9 . t h e d 4 6 b i t c a n b e s e l e c t e d . 1 0 . t h e s o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o n o t a f f e c t t h i s r e g i s t e r . 1 1 . w h e n t h e d 4 6 b i t i s s e t t o 1 ( h a r d w a r e r e s e t 2 w h e n v d e t p a s s e s ) , s e t t h e d 4 7 b i t t o 1 ( b e l o w v d e t ) . ( d o n o t s e t t o 0 ) . b 5 b 4 r w r w r w r w r w r w rw function d 4 6 voltage monitor mode select bit (6) 0: voltage detection interrupt request is generated when passing through vdet 1: hardware reset 2 when passing through vdet r w d47 rw voltage detection interrupt request is generated or hardware reset 2 when vcc passes vdet (9) 0: over vdet 1: below vdet 0 : d i g i t a l f i l t e r e n a b l e m o d e ( d i g i t a l f i l t e r c i r c u i t e n a b l e d ) 1 : d i g i t a l f i l t e r d i s a b l e m o d e ( d i g i t a l f i l t e r c i r c u i t d i s a b l e d ) v o l t a g e d e t e c t i o n d i g i t a l f i l t e r d i s a b l e m o d e s e l e c t b i t voltage detection condition select bit (11) figure 5.9 d4int register 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 24 of 204 rej09b0062-0120 figure 5.10 operation example of voltage detection circuit 5.0 v v cc internal reset signal (d46 bit=1) vc13 bit vc27 bit v det voltage detection interrupt request (d46 bit=0) interrupt acknowledged 5.0 v sampling time (3 to 4 clock) set to 1 by program (voltage detection circuit enabled) interrupt acknowledged the above applies to the following conditions. d4int register d40 bit = 1 (voltage detection interrupt enabled) d4int register d41 bit = 0 (digital filter enabled mode) sampling time : 4 cycles of sampling clock selected in df0 bit to df1 bit fring 1 x 32 sampling time (3 to 4 clock) 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 25 of 204 rej09b0062-0120 v cc internal reset signal(d46 bit = 1) vc13 bit vc27 bit v det voltage detection interrupt request (d46 bit = 0) 5.0v set to "1" by program (voltage detection circuit enabled) interrupt acknowledged the above applies to the following conditions. d4int register d40 = 1 (voltage detection interrupt enabled) d4int register d41 = 1 (digital filter disabled mode) d4int register d47 = 1 ( vcc is below vdet) sampling time : 4 cycles of sampling clock selected in df0 bit to df1 bit cm 10 bit cm10 : cm1 register bit vc13 : vcr1 register bit vc27 : vcr2 register bit d46 : d4int register bit figure 5.11 operation example of voltage detection circuit to get out of stop mode (1) 5.0v v cc vc13 bit vc27 bit v det voltage detection interrupt request (d46 bit = 0) set to "1" by program (voltage detection circuit enabled) interrupt acknowledged the above applies to the following conditions. d4int register d40 bit = 1 (voltage detection interrupt enabled) d4int register d41 bit = 1 (digital filter disabled mode) d4int register d47 bit = 0 (vcc is over vdet) sampling time : 4 cycles of sampling clock selected in df0 bit to df1 bit cm10 bit cm10 : cn1 register bit vc13 : vcr1 register bit vc27 : vcr2 register bit d46 : d4int register bit figure 5.12 operation example of voltage detection circuit to get out of stop mode (2) 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 26 of 204 rej09b0062-0120 5.4.1 voltage detection interrupt figure 5.13 shows the block diagram of voltage detection interrupt generation circuit. refer to 5.4.2, "exiting stop mode on a voltage detection circuit" for getting out of stop mode due to the voltage detection interrupt. a voltage detection interrupt is generated when the input voltage at the v cc pin rises to vdet or more or drops below vdet if all of the following conditions hold true in normal operation mode and wait mode. the vc27 bit in the vcr2 register is set to 1 (voltage detection circuit enabled) the d40 bit in the d4int register is set to 1 (voltage detection interrupt enabled) the d46 bit in the d4int register is set 0 (voltage detection interrupt selected) to use the digital filter (d41 bit in the d4int register is set to 0 ), set the cm14 bit in the cm1 register to "0" (low-speed on-chip oscillator). figure 5.14 shows an operation example of voltage detection interrupt generation circuit. the voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscil- lation stop detection interrupt. the d42 bit in the d4int register becomes 1 when passing through vdet is detected after the volt- age inputted to the v cc pin is up or down. a voltage detection interrupt request is generated when the d42 bit changes state from 0 to 1 . the d42 bit needs to be set to 0 in a program. table 5.2 lists the voltage detection interrupt request generation conditions. it takes 4 cycles of sampling clock until the d42 bit is set to "1" since the voltage which inputs to vcc pin passes vdet. it is possible to set the sampling clock detecting that the voltage applied to the v cc pin has passed through vdet with the df0 to df1 bits in the d4int register. table 5.2 voltage detection interrupt request generation conditions v c 2 7 b i t d40 bit d 4 2 b i t d 4 1 b i t v c 1 3 b i t o p e r a t i o n m o d e 1 w a i t m o d e 1 d46 bit 0 from 0 to 1 (2) from 1 to 0 (2) c m 1 4 b i t 0 n o r m a l o p e r a t i o n m o d e (1 ) 11 0 or 1 0 0 or 1 0 0 0 from 0 to 1 (2) from 1 to 0 (2) n o t e s : 1 . t h e s t a t u s e x c e p t t h e w a i t m o d e a n d s t o p m o d e i s h a n d l e d a s t h e n o r m a l m o d e . ( r e f e r t o c h a p t e r 6 , " c l o c k g e n e r a t i o n c i r c u i t . " ) 2 . r e f e r t o f i g u r e 5 . 1 4 , " o p e r a t i o n e x a m p l e o f v o l t a g e d e t e c t i o n i n t e r r u p t g e n e r a t i o n c i r c u i t " f o r i n t e r r u p t g e n e r a t i o n t i m i n g . 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 27 of 204 rej09b0062-0120 figure 5.13 operation detection interrupt generation block v o l t a g e d e t e c t i o n i n t e r r u p t g e n e r a t i o n c i r c u i t o s c i l l a t i o n s t o p d e t e c t i o n i n t e r r u p t s i g n a l w a t c h d o g t i m e r b l o c k t h i s b i t i s s e t t o 0 ( n o t d e t e c t e d ) b y w r i t i n g a 0 i n a p r o g r a m . d 4 3 d 4 1 c m 1 0 d40 vc27 v c c 1 i n t e r n a l r e f e r e n c e v o l t a g e + - ( c a n c e l l e r w i d t h : 2 0 0 n s ) v c 1 3 v o l t a g e d e t e c t i o n s i g n a l i s h w h e n v c 2 7 b i t = 0 ( d i s a b l e d ) noise rejection circuit digital filter f r i n g - s d 4 2 df1 to df0 1/2 = 0 0 2 = 0 1 2 = 1 0 2 = 1 1 2 1/2 1 / 2 n o i s e c a n c e l l e r voltage detection signal w a t c h d o g t i m e r u n d e r f l o w s i g n a l d42 bit is set to 0 (not detected) by writing a 0 in a program. when vc27 bit is set to 0 (voltage detection circuit disabled), d42 bit is set to 0 . v o l t a g e d e t e c t i o n c i r c u i t voltage detection interrupt signal watchdog timer interrupt signal n o n - m a s k a b l e i n t e r r u p t s i g n a l d46 h a r d w a r e r e s e t 2 d 4 0 , d 4 1 , d 4 2 , d 4 3 , d f 0 , d f 1 , d 4 6 , d 4 7 : b i t s i n d 4 i n t r e g i s t e r c m 0 2 : b i t i n c m 0 r e g i s t e r v c 1 3 : b i t i n v c r 1 r e g i s t e r c m 1 0 : b i t i n c m 1 r e g i s t e r v c 2 7 : b i t i n v c r 2 r e g i s t e r d47 figure 5.14 voltage detection interrupt generation circuit operation example o u t p u t o f d i g i t a l f i l t e r ( 2 ) d 4 2 b i t d 4 2: b i t i n d 4 i n t r e g i s t e r v c 1 3: b i t i n v c r 1 r e g i s t e r v o l t a g e d e t e c t i o n i n t e r r u p t s i g n a l n o v o l t a g e d e t e c t i o n i n t e r r u p t s i g n a l s a r e g e n e r a t e d w h e n d 4 2 b i t i s h . s a m p l i n g set d42 bit to 0 in a program (not detected) vc13 bit vcc sampling sampling s a m p l i n g s e t d 4 2 b i t t o 0 i n a p r o g r a m ( n o t d e t e c t e d ) n o t e s : 1 . d 4 0 i s 1 ( v o l t a g e d e t e c t i o n i n t e r r u p t e n a b l e d ) . 2 . o u t p u t o f t h e d i g i t a l f i l t e r s h o w n i n f i g u r e 5 . 1 1 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 28 of 204 rej09b0062-0120 5.4.2 exiting stop mode on a voltage detection interrupt a voltage detection interrupt is generated when the input voltage at the v cc pin rises to vdet or more or drops below vdet if all of the following conditions hold true in stop mode. the vc27 bit in the vcr2 register is set to 1 (voltage detection circuit enabled) the d40 bit in the d4int register is set to 1 (voltage detection interrupt enabled) the d41 bit in the d4int register is set 1 (digital filter disabled mode) the d46 bit in the d4int register is set 0 (voltage detection interrupt selected) the voltage detection interrupt shares the interrupt vector with the watchdog timer interrupt and oscil- lation stop detection interrupt. the d42 bit in the d4int register becomes 1 when passing through vdet is detected after the volt- age inputted to the v cc pin is up or down. a voltage detection interrupt request is generated when the d42 bit changes state from 0 to 1 . the d42 bit needs to be set to 0 in a program. table 5.3 lists the voltage detection interrupt request generation conditions to get out of stop mode. table 5.3 voltage detection interrupt request generation conditions to get out of stop mode v c 2 7 b i t d40 bit d 4 2 b i t d41 bit v c 1 3 b i t o p e r a t i o n m o d e 11 d 4 6 b i t 0 from 0 to 1 from 1 to 0 stop mode notes: 1. the status except the wait mode and stop mode is handled as the normal mode. (refer to chapter 6, "clock generation circuit.") 2. refer to figure 5.14, "operation example of voltage detection interrupt generation circuit" for interrupt generation timing. 1 0 d47 bit 0 or 1 5.4 voltage detection circuit
r8c/11 group rev.1.20 jan 27, 2006 page 29 of 204 rej09b0062-0120 c p u c l o c k s o u r c e p e r i p h e r a l f u n c t i o n c l o c k s o u r c e u s e o f c l o c k main clock oscillation circuit i t e m c l o c k f r e q u e n c y 0 t o 2 0 m h z c e r a m i c r e s o n a t o r c r y s t a l o s c i l l a t o r u s a b l e o s c i l l a t o r x in , x out (1) p i n s t o c o n n e c t o s c i l l a t o r present oscillation starts and sto p s sto pp ed oscillator status after reset externally derived clock can be in p ut other o n - c h i p o s c i l l a t o r c p u c l o c k s o u r c e p e r i p h e r a l f u n c t i o n c l o c k s o u r c e c p u a n d p e r i p h e r a l f u n c t i o n c l o c k s o u r c e s w h e n t h e m a i n c l o c k s t o p s o s c i l l a t i n g a pp rox. 8 mhz present sto pp ed n o t e s : 1 . c a n b e u s e d a s p 4 6 a n d p 4 7 w h e n t h e o n - c h i p o s c i l l a t o r c l o c k i s u s e d f o r c p u c l o c k w h i l e t h e m a i n c l o c k o s c i l l a t i o n c i r c u i t i s n o t u s e d . h i g h - s p e e d o n - c h i p o s c i l l a t o r low-s p eed on-chi p oscillator cpu clock source peripheral function clock source cpu and peripheral function clock sources when the main clock sto p s oscillatin g a pp rox. 125 khz present oscillatin g (n ote 1 ) (n ote 1 ) 6. clock generation circuit the clock generation circuit contains two oscillator circuits as follows: main clock oscillation circuit on-chip oscillator (with oscillation stop detection function) table 6.1 lists the clock generation circuit specifications. figure 6.1 shows the clock generation circuit. figures 6.2 to 6.4 show the clock-related registers. table 6.1 clock generation circuit specifications 6. clock generating circuit
r8c/11 group rev.1.20 jan 27, 2006 page 30 of 204 rej09b0062-0120 c p u c l o c k i n t e r r u p t r e q u e s t l e v e l j u d g m e n t o u t p u t h a r d w a r e r e s e t 2 c m 1 0 = 1 ( s t o p m o d e ) w a i t i n s t r u c t i o n o n - c h i p o s c i l l a t o r c l o c k m a i n c l o c k c m 0 5 r e s e t r q s c r c m 0 2 q s r x o u t x i n f a d a d f 8 f 3 2 c b o c d 2 = 0 o c d 2 = 1 c m 1 4 f 8 s i o f 3 2 s i o f 1 f r i n g 1 / 1 2 8 f r i n g 1 2 8 f 1 s i o e f 2 e c m 1 3 c m 0 2 , c m 0 5 , c m 0 6 : b i t s i n c m 0 r e g i s t e r c m 1 0 , c m 1 3 , c m 1 4 , c m 1 6 , c m 1 7 : b i t s i n c m 1 r e g i s t e r o c d 0 , o c d 1 , o c d 2 : b i t s i n o c d r e g i s t e r h r 0 0 , h r 0 1 : b i t s i n h r 0 r e g i s t e r d e t a i l s o f d i v i d e r 1 / 2 1 / 2 1 / 2 1 / 2 c m 0 6 = 0 c m 1 7 t o c m 1 6 = 0 0 2 c m 0 6 = 0 c m 1 7 t o c m 1 6 = 0 1 2 c m 0 6 = 0 c m 1 7 t o c m 1 6 = 1 0 2 c m 0 6 = 1 c m 0 6 = 0 c m 1 7 t o c m 1 6 = 1 1 2 d a b 1 / 2 c f o r c i b l e d i s c h a r g e w h e n o c d 0 (1 ) = 0 o c d 2 b i t s w i t c h s i g n a l o c d 1 (1 ) c m 1 4 b i t s w i t c h s i g n a l p u l s e g e n e r a t i o n c i r c u i t f o r c l o c k e d g e d e t e c t i o n a n d c h a r g e , d i s c h a r g e c o n t r o l c i r c u i t c h a r g e , d i s c h a r g e c i r c u i t n o t e s : 1 . s e t t h e s a m e v a l u e t o t h e o c d 1 b i t a n d o c d 0 b i t . o s c i l l a t i o n s t o p d e t e c t i o n i n t e r r u p t g e n e r a t i o n c i r c u i t m a i n c l o c k w a t c h d o g t i m e r i n t e r r u p t o s c i l l a t i o n s t o p d e t e c t i o n , w a t c h d o g t i m e r , v o l t a g e d e t e c t i o n i n t e r r u p t o s c i l l a t i o n s t o p d e t e c t i o n c i r c u i t o s c i l l a t i o n s t o p d e t e c t i o n d i v i d e r p e r i p h e r a l f u n c t i o n c l o c k ? ? ? ? ? ? ? ? ? ? ? ? figure 6.1 clock generation circuit 6. clock generating circuit
r8c/11 group rev.1.20 jan 27, 2006 page 31 of 204 rej09b0062-0120 s y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( 1 ) s y m b o la d d r e s sa f t e r r e s e t c m 00 0 0 6 1 6 6 8 1 6 bit name f u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 s e t t o 0 c m 0 5 ( b 3 ) ( b 1 - b 0 ) c m 0 2 c m 0 6 r e s e r v e d b i t w a i t p e r i p h e r a l f u n c t i o n c l o c k s t o p b i t 0 : d o n o t s t o p p e r i p h e r a l f u n c t i o n c l o c k i n w a i t m o d e 1 : s t o p p e r i p h e r a l f u n c t i o n c l o c k i n w a i t m o d e r e s e r v e d b i ts e t t o 1 r e s e r v e d b i t s e t t o 0 m a i n c l o c k ( x i n - x o u t ) s t o p b i t (2 , 4 ) 0 : o n 1 : o f f (3 ) c p u c l o c k d i v i s i o n s e l e c t b i t 0 (5 ) 0 : c m 1 6 a n d c m 1 7 v a l i d 1 : d i v i d e - b y - 8 m o d e r e s e r v e d b i ts e t t o 0 n o t e s : 1 . s e t t h e p r c 0 b i t o f p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 . t h e c m 0 5 b i t i s p r o v i d e d t o s t o p t h e m a i n c l o c k w h e n t h e o n - c h i p o s c i l l a t o r m o d e i s s e l e c t e d . t h i s b i t c a n n o t b e u s e d f o r d e t e c t i o n a s t o w h e t h e r t h e m a i n c l o c k s t o p p e d o r n o t . t o s t o p t h e m a i n c l o c k , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d : ( 1 ) s e t t h e o c d 0 a n d o c d 1 b i t s i n t h e o c d r e g i s t e r t o 0 0 2 ( d i s a b l i n g o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n ) . ( 2 ) s e t t h e o c d 2 b i t t o 1 ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) . 3 . s e t t h e c m 0 5 b i t t o 1 ( m a i n c l o c k s t o p s ) a n d t h e c m 1 3 b i t i n t h e c m 1 r e g i s t e r t o 1 ( x i n - x o u t p i n ) w h e n t h e e x t e r n a l c l o c k i s i n p u t . 4 . w h e n t h e c m 0 5 b i t i s s e t t o 1 ( m a i n c l o c k s t o p ) , p 4 6 a n d p 4 7 c a n b e u s e d a s i n p u t p o r t s . 5 . w h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e , t h e c m 0 6 b i t i s s e t t o 1 ( d i v i d e - b y - 8 m o d e ) . r w r w r w r w r w r w r w r w 0000 1 ( b 4 ) (b7) figure 6.2 cm0 register and cm1 register system clock control register 1 (1) s y m b o la d d r e s sa f t e r r e s e t c m 10 0 0 7 1 6 2 0 1 6 b i t n a m e function b i t s y m b o l b 7 b 6b 5b 4 b 3b 2b 1b 0 c m 1 0 all clock stop control bit (4, 7) 0 : c l o c k o n 1 : a l l c l o c k s o f f ( s t o p m o d e ) n o t e s : 1 . w r i t e t o t h i s r e g i s t e r a f t e r s e t t i n g t h e p r c 0 b i t o f p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e ) . 2 . w h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e , t h e c m 1 5 b i t i s s e t t o 1 ( d r i v e c a p a c i t y h i g h ) . 3 . e f f e c t i v e w h e n t h e c m 0 6 b i t i s 0 ( c m 1 6 a n d c m 1 7 b i t s e n a b l e ) . 4 . i f t h e c m 1 0 b i t i s 1 ( s t o p m o d e ) , t h e i n t e r n a l f e e d b a c k r e s i s t o r b e c o m e s i n e f f e c t i v e . 5 . t h e c m 1 4 b i t c a n b e s e t t o 1 ( l o w - s p e e d o n - c h i p o s c i l l a t o r o f f ) i f t h e o c d 2 b i t = 0 ( s e l e c t i n g m a i n c l o c k ) . w h e n t h e o c d 2 b i t i s s e t t o 1 ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) , t h e c m 1 4 b i t i s s e t t o 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) . t h i s b i t r e m a i n s u n c h a n g e d w h e n 1 i s w r i t t e n . 6 . w h e n u s i n g v o l t a g e d e t e c t i o n i n t e r r u p t c i r c u i t , c m 1 4 b i t i s s e t t o " 0 " . 7 . w h e n t h e c m 1 0 b i t i s s e t t o 1 ( s t o p m o d e ) o r t h e c m 0 5 b i t i n t h e c m 0 r e g i s t e r t o 1 ( m a i n c l o c k s t o p s ) a n d t h e c m 1 3 b i t i s s e t t o 1 ( x i n - x o u t p i n ) , t h e x o u t ( p 4 7 ) p i n b e c o m e s h . w h e n t h e c m 1 3 b i t i s s e t t o 0 ( i n p u t p o r t p 4 6 , p 4 7 ) , t h e p 4 7 i s i n i n p u t s t a t e . r w r e s e r v e d b i t s e t t o 0 0 0 c m 1 5 x in -x out drive capacity select bit (2) 0 : l o w 1 : h i g h c m 1 6 c m 1 7 cpu clock division select bit 1 (3) 0 0 : n o d i v i s i o n m o d e 0 1 : d i v i s i o n b y 2 m o d e 1 0 : d i v i s i o n b y 4 m o d e 1 1 : d i v i s i o n b y 1 6 m o d e b 7 b 6 r w r w r w ( b 2 ) p o r t x i n - x o u t s w i t c h b i t (7 ) c m 1 4 low-speed on-chip oscillation stop bit (5, 6) 0 : l o w - s p e e d o n - c h i p o s c i l l a t o r o n 1 : l o w - s p e e d o n - c h i p o s c i l l a t o r o f f r w r e s e r v e d b i t s e t t o 0 ( b 1 ) c m 1 3 0 : i n p u t p o r t p 4 6 , p 4 7 1 : x i n - x o u t p i n r w r w r w r w 6. clock generating circuit
r8c/11 group rev.1.20 jan 27, 2006 page 32 of 204 rej09b0062-0120 figure 6.3 ocd register r w r w r w r o b 7b 6b 5b 4b 3b 2b 1b0 ocd0 ocd1 ocd2 ocd3 0 00 0 o s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e r ( 1 ) symbol address after reset ocd 0 0 0 c 1 6 04 16 bit name function b i t s y m b o l s y s t e m c l o c k s e l e c t b i t (6 ) 0 0 : t h e f u n c t i o n i s d i s a b l e d (4 ) 0 1 : a v o i d t h i s s e t t i n g 1 0 : a v o i d t h i s s e t t i n g 1 1 : t h e f u n c t i o n i s e n a b l e d (7 ) 0 : s e l e c t m a i n c l o c k (7 ) 1 : s e l e c t o n - c h i p o s c i l l a t o r c l o c k (2 ) 0 : m a i n c l o c k o n 1 : m a i n c l o c k o f f o s c i l l a t i o n s t o p d e t e c t i o n e n a b l e b i t c l o c k m o n i t o r b i t (3 , 5 ) reserved bit set to "0" n o t e s : 1 . s e t t h e p r c 0 b i t i n t h e p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r . 2 . t h e o c d 2 b i t i s s e t t o 1 ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) a u t o m a t i c a l l y i f a m a i n c l o c k o s c i l l a t i o n s t o p i s d e t e c t e d w h i l e t h e o c d 1 t o o c d 0 b i t s a r e s e t t o 1 1 2 ( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n e n a b l e d ) . i f t h e o c d 3 b i t i s s e t t o 1 ( m a i n c l o c k s t o p ) , t h e o c d 2 b i t r e m a i n s u n c h a n g e d w h e n t r y i n g t o w r i t e 0 ( s e l e c t i n g m a i n c l o c k ) . 3 . t h e o c d 3 b i t i s e n a b l e d w h e n t h e o c d 1 t o o c d 0 b i t s a r e s e t t o 1 1 2 ( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n e n a b l e d ) . 4 . t h e o c d 1 t o o c d 0 b i t s s h o u l d b e s e t t o 0 0 2 ( o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n d i s a b l e d ) b e f o r e e n t e r i n g s t o p m o d e o r o n - c h i p o s c i l l a t o r ( m a i n c l o c k s t o p s ) . 5 . t h e o c d 3 b i t r e m a i n s s e t t o 0 ( m a i n c l o c k o n ) i f t h e o c d 1 t o o c d 0 b i t s a r e s e t t o 0 0 2 . 6 . t h e c m 1 4 b i t g o e s t o 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) i f t h e o c d 2 b i t i s s e t t o 1 ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) . 7 . r e f e r t o f i g u r e 6 . 7 s w i t c h i n g c l o c k s o u r c e f r o m l o w - s p e e d o n - c h i p o s c i l l a t o r t o m a i n c l o c k f o r t h e s w i t c h i n g p r o c e d u r e w h e n t h e m a i n c l o c k r e - o s c i l l a t e s a f t e r d e t e c t i n g a n o s c i l l a t i o n s t o p . b 1 b 0 (b7-b4) r w 6. clock generating circuit
r8c/11 group rev.1.20 jan 27, 2006 page 33 of 204 rej09b0062-0120 figure 6.4 hr0 register and hr1 register h i g h - s p e e d o n - c h i p o s c i l l a t o r c o n t r o l r e g i s t e r 0 ( 3 ) s y m b o la d d r e s sa f t e r r e s e t h r 00 0 0 8 1 6 0 0 1 6 bit name function b i t s y m b o l b 7b 6 b 5b 4b 3 b 2b 1b 0 h r 0 0 high-speed on-chip oscillator enable bit 0: high-speed on-chip oscillator off 1: high-speed on-chip oscillator on r w reserved bit set to 0 0 0 ( b 7 - b 2 ) h i g h - s p e e d o n - c h i p o s c i l l a t o r s e l e c t b i t (1 ) 0: low-speed on-chip oscillator selected (2) 1: high-speed on-chip oscillator selected h r 0 1 r w r w r w high-speed on-chip oscillator control register 1 (1) s y m b o la d d r e s sa f t e r r e s e t h r 10 0 0 b 1 6 4 0 1 6 f u n c t i o n b 7b 6b 5 b 4b 3b 2 b 1b 0 the frequency of high-speed on-chip oscillator is adjusted with bits 0 to bits 6. period of high-speed on-chip oscillator = td(hr offset) + (64 ? ? ? ? ? ? ? 0 . r w 0 r w 0 0 0 0 0 n o t e s : 1 . s e t t h e p r c 0 b i t i n t h e p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r . n o t e s : 1 . t h e h r 0 1 b i t s h o u l d b e c h a n g e d u n d e r t h e f o l l o w i n g c o n d i t i o n s . h r 0 0 = 1 ( h i g h - s p e e d o n - c h i p o s c i l l a t o r o n ) c m 1 r e g i s t e r c m 1 4 b i t = 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) 2 . w h e n w r i t i n g 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r s e l e c t e d ) t o t h e h r 0 1 b i t , d o n o t w r i t e 0 ( h i g h - s p e e d o n - c h i p o s c i l l a t o r s t o p s ) t o t h e h r 0 0 b i t s i m u l t a n e o u s l y . s e t t h e h r 0 0 b i t t o 0 a f t e r s e t t i n g t h e h r 0 1 b i t t o 0 . 3 . s e t t h e p r c 0 b i t i n t h e p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e ) b e f o r e r e w r i t i n g t h i s r e g i s t e r . 6. clock generating circuit
r8c/11 group rev.1.20 jan 27, 2006 page 34 of 204 rej09b0062-0120 microcomputer (built-in feedback resistor) x i n x out e x t e r n a l l y d e r i v e d c l o c k o p e n vcc v s s microcomputer (built-in feedback resistor) x i n x o u t r d c in c o u t (note 1) n o t e s : 1 .i n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . t h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g . u s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r . w h e n t h e o s c i l l a t i o n d r i v e c a p a c i t y i s s e t t o l o w , c h e c k t h a t o s c i l l a t i o n i s s t a b l e . a l s o , i f t h e o s c i l l a t o r m a n u f a c t u r e r ' s d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p , i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n x i n a n d x o u t f o l l o w i n g t h e i n s t r u c t i o n . figure 6.5 examples of main clock connection circuit the following describes the clocks generated by the clock generation circuit. 6.1 main clock this clock is supplied by a main clock oscillation circuit. this clock is used as the clock source for the cpu and peripheral function clocks. the main clock oscillator circuit is configured by connecting a resonator between the x in and x out pins. the main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power con- sumed in the chip. the main clock oscillator circuit may also be configured by feeding an externally generated clock to the x in pin. figure 6.5 shows examples of main clock connection circuit. during reset and after reset, the main clock is turned off. the main clock starts oscillating when the cm05 bit in the cm0 register is set to 0 (main clock on) after setting the cm13 bit in the cm1 register to 1 (x in - x out pin). to use the main clock for the cpu clock, set the ocd2 bit in the ocd register to 0 (selecting main clock) after the main clock becomes oscillating stably. the power consumption can be reduced by setting the cm05 bit in the cm0 register to 1 (main clock off) if the ocd2 bit is set to 1 (selecting on-chip oscillator clock). note that if an externally generated clock is fed into the x in pin, the main clock cannot be turned off by setting the cm05 bit to 1 . if necessary, use an external circuit to turn off the clock. during stop mode, all clocks including the main clock are turned off. refer to section 6.4, power con- trol. 6.1 main clock
r8c/11 group rev.1.20 jan 27, 2006 page 35 of 204 rej09b0062-0120 6.2 on-chip oscillator clock this clock is supplied by an on-chip oscillator. there are two kinds of on-chip oscillator: high-speed on- chip oscillator and low-speed on-chip oscillator. these oscillators are selected by the bit hr01 bit in the hr0 register. 6.2.1 low-speed on-chip oscillator clock the clock derived from the low-speed on-chip oscillator is used as the clock source for the cpu clock, peripheral function clock, f ring , f ring128 and f ring-s . after reset, the on-chip oscillator clock derived from low-speed on-chip oscillator by divided by 8 is selected for the cpu clock. if the main clock stops oscillating when the ocd1 to ocd0 bits in the ocd register are 11 2 (oscilla- tion stop detection function enabled), the low-speed on-chip oscillator automatically starts operating, supplying the necessary clock for the microcomputer. the frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operation ambient temperature. the application products must be designed with sufficient margin for the frequency change. 6.2.2 high-speed on-chip oscillator clock the clock derived from high-speed on-chip oscillator is used as the clock source for the cpu clock, peripheral function clock, f ring , f ring128 , and f ring1-fast . after reset, the on-chip oscillator clock derived from high-speed on-chip oscillator is halted. the oscil- lation is started by setting the hr00 bit in the hr0 register to 1 (high-speed on-chip oscillator on). the frequency can be adjusted by the hr1 register. the relationship between the value of hr1 register and the period of high-speed on-chip oscillator is shown below. it is noted that the difference in delay between the bits should be adjusted by changing each bit. bit 7 should be set be 0 . period of high-speed on-chip oscillator = td(hr offset) + (64 5 b6 + 32 5 b5 + 16 5 b4 + 8 5 b3 + 4 ? ?
r8c/11 group rev.1.20 jan 27, 2006 page 36 of 204 rej09b0062-0120 6.3 cpu clock and peripheral function clock there are two types of clocks: cpu clock to operate the cpu and peripheral function clock to operate the peripheral functions. also refer to figure 6.1 clock generation circuit . 6.3.1 cpu clock this is an operating clock for the cpu and watchdog timer. the clock source for the cpu clock can be chosen to be the main clock or on-chip oscillator clock. the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the cpu clock. use the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register to select the divide- by-n value. after reset, the low-speed on-chip oscillator clock divided by 8 provides the cpu clock. note that when entering stop mode from high or middle speed mode, the cm06 bit is set to 1 (divide- by-8 mode). 6.3.2 peripheral function clock (f 1 , f 2 , f 8 , f 32 , f ad , f 1sio , f 8sio , f 32sio , f ring , f ring128 ) these are operating clocks for the peripheral functions. of these, fi (i=1, 2, 8, 32) is derived from the main clock or on-chip oscillator clock by dividing them by i. the clock fi is used for timers x, y, z and c. the clock fj sio (j=1, 8, 32) is derived from the main clock or on-chip oscillator clock by dividing them by j. the clock fj sio is used for serial interface. the f ad clock is produced from the main clock or the on-chip oscillator clock and is used for the a/d converter. when the wait instruction is executed after setting the cm02 bit in the cm0 register to 1 (peripheral function clock turned off during wait mode), the clocks fi, fj sio , and f ad are turned off. 6.3.3 f ring and f ring128 these are operating clocks for the peripheral functions. the f ring runs at the same frequency as the on-chip oscillator, and can be used as the souce for the timer y. the f ring128 is derived from the f ring by dividing it by 128, and can be used for timer c. when the wait instruction is executed, the clocks f ring and f ring128 are not turned off. 6.3.4 f ring -fast this is used as the count source for the timer c. the f ring -fast is derived from the high-speed on-chip oscillator and provided by setting the hr00 bit to 1 (high-speed on-chip oscillator on). when the wait instruction is executed, the clock f ring -fast is not turned off. 6.3 cpu clock and peripheral function clock
r8c/11 group rev.1.20 jan 27, 2006 page 37 of 204 rej09b0062-0120 6.4 power control there are three power control modes. all modes other than wait and stop modes are referred to as normal operation mode. 6.4.1 normal operation mode normal operation mode is further classified into four modes. in normal operation mode, because the cpu clock and the peripheral function clocks both are on, the cpu and the peripheral functions are operating. power control is exercised by controlling the cpu clock frequency. the higher the cpu clock frequency, the greater the processing capability. the lower the cpu clock frequency, the smaller the power consumption in the chip. if the unnecessary oscillator circuits are turned off, the power consumption is further reduced. before the clock sources for the cpu clock can be switched over, the new clock source to which switched must be oscillating stably. if the new clock source is the main clock, allow a sufficient wait time in a program until it becomes oscillating stably. high-speed mode the main clock divided by 1 (undivided) provides the cpu clock. if the cm14 bit is set to 0 (low- speed on-chip oscillator on) or the hr00 bit in the hr0 register is set to 1 (high-speed on-chip oscillator on), the f ring and f ring128 can be used for timers y and c. when the hr00 bit is set to 1 , f ring- fast can be used for timer c. medium-speed mode the main clock divided by 2, 4, 8 or 16 provides the cpu clock. if the cm14 bit is set to 0 (low- speed on-chip oscillator on) or the hr00 bit in the hr0 register is set to 1 (high-speed on-chip oscillator on), the f ring and f ring128 can be used for timers y and c. when the hr00 bit is set to 1 , f ring- fast can be used for timer c. high-speed, low-speed, on-chip oscillator mode the on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the cpu clock. the on- chip oscillator clock is also the clock source for the peripheral function clocks. when the hr00 bit is set to 1 , f ring- fast can be used for timer c. 6.4 power control
r8c/11 group rev.1.20 jan 27, 2006 page 38 of 204 rej09b0062-0120 table 6.2 setting clock related bit and modes m o d e s o c d r e g i s t e r ocd2 cm1 register c m 1 7 , c m 1 6 c m 0 r e g i s t e r c m 0 6c m 0 5 h i g h - s p e e d m o d e 000 2 00 m e d i u m - s p e e d m o d e 001 2 00 010 2 00 d i v i d e d b y 2 010 011 2 00 h i g h - s p e e d , l o w - s p e e d o n - c h i p o s c i l l a t o r m o d e d i v i d e d b y 4 d i v i d e d b y 8 d i v i d e d b y 1 6 n o t e s : 1 . t h e l o w - s p e e d o n - c h i p o s c i l l a t o r i s u s e d a s t h e o n - c h i p o s c i l l a t o r c l o c k w h e n t h e c m 1 r e g i s t e r c m 1 4 b i t = 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) a n d h r 0 r e g i s t e r h r 0 1 b i t = 0 ( l o w - s p e e d o n - c h i p o s c i l l a t o r s e l e c t e d ) . t h e h i g h - s p e e d o n - c h i p o s c i l l a t o r i s u s e d a s t h e o n - c h i p o s c i l l a t o r c l o c k w h e n t h e h r 0 r e g i s t e r h r 0 0 b i t = 1 ( h i g h - s p e e d o n - c h i p o s c i l l a t o r o n ) a n d h r 0 1 b i t = 1 ( h i g h - s p e e d o n - c h i p o s c i l l a t o r s e l e c t e d ) . 101 2 00 o r 1 110 2 00 o r 1 110 o r 1 111 2 00 o r 1 100 2 00 o r 1 d i v i d e d b y 2 d i v i d e d b y 4 d i v i d e d b y 8 d i v i d e d b y 1 6 n o d i v i s i o n ( 1 ) c m 1 3 1 1 1 1 1 6.4 power control
r8c/11 group rev.1.20 jan 27, 2006 page 39 of 204 rej09b0062-0120 interrupt cm02=0 cm02=1 serial interface interrupt can be used when operating with internal or external clock can be used when operating with external clock key input interrupt can be used can be used a/d conversion interrupt can be used in one-shot mode timer x interrupt can be used in all modes can be used in event counter mode timer y interrupt (do not use) can be used when counting inputs from cntr1 pin in timer mode can be used in all modes int interrupt can be used can be used (int0 and int3 can be used if there is no filter. voltage detection interrupt can be used can be used oscillation stop detection interrupt can be used (do not use) timer z interrupt can be used in all modes (do not use) timer c interrupt can be used in all modes (do not use) table 6.3 interrupts to exit wait mode and usage conditions 6.4.2 wait mode in wait mode, the cpu clock is turned off, so are the cpu and the watchdog timer because both are operated by the cpu clock. because the main clock and on-chip oscillator clock both are on, the peripheral functions using these clocks keep operating. peripheral function clock stop function if the cm02 bit is 1 (peripheral function clocks turned off during wait mode), the f 1 , f 2 , f 8 , f 32 , f 1sio , f 8sio , f 32sio , and f ad clocks are turned off when in wait mode, with the power consumption reduced that much. entering wait mode the microcomputer is placed into wait mode by executing the wait instruction. pin status during wait mode the status before wait mode is retained. exiting wait mode the microcomputer is moved out of wait mode by a hardware reset or peripheral function interrupt. when using a hardware reset to exit wait mode, set the ilvl2 to ilvl0 bits for the peripheral function interrupts to 000 2 (interrupts disabled) before executing the wait instruction. the peripheral function interrupts are affected by the cm02 bit. if cm02 bit is 0 (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. if cm02 bit is 1 (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to exit from wait mode. table 6. 3 lists the interrupts to exit wait mode and the usage conditions. when using a peripheral function interrupt to exit wait mode, set up the following before executing the wait instruction. 1. in the ilvl2 to ilvl0 bits in the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit wait mode. also, for all of the peripheral function interrupts not used to exit wait mode, set the ilvl2 to ilvl0 bits to 000 2 (interrupt disable). 2. set the i flag to 1 . 3. enable the peripheral function whose interrupt is to be used to exit wait mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt sequence is executed. the cpu clock turned on when exiting wait mode by a peripheral function interrupt is the same cpu clock that was on when the wait instruction was executed. 6.4 power control
r8c/11 group rev.1.20 jan 27, 2006 page 40 of 204 rej09b0062-0120 6.4.3 stop mode in stop mode, all oscillator circuits are turned off, so are the cpu clock and the peripheral function clocks. therefore, the cpu and the peripheral functions clocked by these clocks stop operating. the least amount of power is consumed in this mode. if the voltage applied to vcc pin is v ram or more, the internal ram is retained. however, the peripheral functions clocked by external signals keep operating. the following interrupts can be used to exit stop mode. key interrupt ______ ______ ______ int0 to int2 interrupts (int0 can be used only when there is no filter.) int3 interrupt (int3 can be used when there is no filter and timer c output compare mode (the tcc13 bit in the tcc1 register is set to 1 )) timer x interrupt (when counting external pulses in event counter mode) timer y interrupt (when counting inputs from cntr1 pin in timer mode) serial interface interrupt (when external clock is selected) voltage detection interrupt entering stop mode the microcomputer is placed into stop mode by setting the cm10 bit of cm1 register to 1 (all clocks turned off). at the same time, the cm06 bit of cm0 register is set to 1 (divide-by-8 mode) and the cm15 bit of cm10 register is set to 1 (main clock oscillator circuit drive capability high). before entering stop mode, set the ocd1 to ocd0 bits to 00 2 (oscillation stop detection function disable). pin status in stop mode the status before wait mode is retained. however, the x out (p4 7 ) pin is held h when the cm13 bit in the cm1 register is set to 1 (x in -x out pin). the p4 7 (x out ) is in input state when the cm13 bit is set to 0 (input port p4 6 , p4 7 ). exiting stop mode the microcomputer is moved out of stop mode by a hardware reset or peripheral function interrupt. when using a hardware reset to exit stop mode, set the ilvl2 to ilvl0 bits for the peripheral function interrupts to 000 2 (interrupts disabled) before setting the cm10 bit to 1 . when using a peripheral function interrupt to exit stop mode, set up the following before setting the cm10 bit to 1 . 1. in the ilvl2 to ilvl0 bits in the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. also, for all of the peripheral function interrupts not used to exit stop mode, set the ilvl2 to ilvl0 bits to 000 2 . 2. set the i flag to 1 . 3. enable the peripheral function whose interrupt is to be used to exit stop mode. in this case, when an interrupt request is generated and the cpu clock is thereby turned on, an interrupt sequence is executed. the main clock divided by 8 of the clock which is used right before stop mode is used for the cpu clock when exiting stop mode by a peripheral function interrupt. 6.4 power control
r8c/11 group rev.1.20 jan 27, 2006 page 41 of 204 rej09b0062-0120 figure 6.6 state transition of power control figure 6.6 shows the state transition of power control. 6.4 power control low-speed on-chip oscillator mode ocd2=1 hr01=0 cm14=0 there are six power control modes. (1) high-speed mode (2) middle-speed mode (3) high-speed on-chip oscillator mode (4) low-speed on-chip oscillator mode (5) wait mode (6) stop mode cm05: bit in cm0 register cm10, cm13, cm14: bit in cm1 register ocd2: bit in ocd register hr00, hr01: bit in hr0 register high-speed mode, middle-speed mode ocd2=0 cm05=0 cm13=1 high-speed on-chip oscillator mode ocd2=1 hr01=1 hr00=1 reset wait mode wait instruction cm 14= 0 , hr 01 =0 , o c d2= 1 c m 1 3=1 , cm 0 5=0, o cd2= 0 hr00 =1, hr01=1 , ocd2=1 cm1 3=1, cm0 5=0, ocd2=0 interrupt stop mode cm10=1 (all clocks stop) interrupt cm14=0, hr01=0 hr00=1, hr01=1
r8c/11 group rev.1.20 jan 27, 2006 page 42 of 204 rej09b0062-0120 6.5 oscillation stop detection function the oscillation stop detection function is such that main clock oscillation circuit stop is detected. the oscillation stop detection function can be enabled and disabled by the ocd1 to ocd0 bits in the ocd register. table 6.4 lists the specifications of the oscillation stop detection function. where the main clock corresponds to the cpu clock source and the ocd1 to ocd0 bits are 11 2 (oscillation stop detection function enabled), the system is placed in the following state if the main clock comes to a halt: ocd register ocd2 bit = 1 (selecting on-chip oscillator clock) ocd register ocd3 bit = 1 (main clock stopped) cm1 register cm14 bit = 0 (low-speed on-chip oscillator oscillating) oscillation stop detection interrupt request occurs table 6.4 oscillation stop detection function specifications item specification oscillation stop detectable clock and f(x in ) 11 2 (oscillation stop detection detection function function enabled) operation at oscillation stop detection oscillation stop detection interrupt occurs 6.5.1 how to use oscillation stop detection function the oscillation stop detection interrupt shares the vector with the watchdog timer interrupt. if the oscillation stop detection and watchdog timer interrupts both are used, the interrupt factor must be determined. table 6.5 shows how to determine the interrupt factor with the oscillation stop detection interrupt, watchdog timer interrupt and voltage detection interrupt. where the main clock re-oscillated after oscillation stop, the clock source for the cpu clock and peripheral functions must be switched to the main clock in the program. figure 6.7 shows the procedure for switching the clock source from the low-speed on-chip oscillator to the main clock. to enter wait mode while using the oscillation stop detection function, set the cm02 bit to 0 (periph- eral function clocks not turned off during wait mode). since the oscillation stop detection function is provided in preparation for main clock stop due to external factors, set the ocd1 to ocd0 bits to 00 2 (oscillation stop detection function disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is selected or the cm05 bit is altered. this function cannot be used when the main clock frequency is below 2 mhz. set the ocd1 to ocd0 bits to 00 2 (oscillation stop detection function disabled). when using the low-speed on-chip oscillator clock for the cpu clock and clock sources of peripheral functions after detecting the oscillation stop, set the hr01 bit in the hr0 register to 0 (low-speed on-chip oscillator selected) and the ocd1 to ocd0 bits to 11 2 (oscillation stop detection function enabled). when using the high-speed on-chip oscillator clock for the cpu clock and clock sources of peripheral functions after detecting the oscillation stop, set the hr01 bit to 1 (high-speed on-chip oscillator selected) and the ocd1 to ocd0 bits to 11 2 (oscillation stop detection function enabled). 6.5 oscillation stop detection function
r8c/11 group rev.1.20 jan 27, 2006 page 43 of 204 rej09b0062-0120 figure 6.7 switching clock source from low-speed on-chip oscillator to main clock switch to main clock verify ocd3 bit determine several times 1(main clock stop) 0(main clock oscillating) determine several times that the main clock is supplied set ocd2 bit to 0 (selecting main clock) ocd3 to ocd0 bits: bits in ocd register end set ocd1 to ocd0 bits to 00 2 (oscillation stop detection function disabled) table 6.5 determination of interrupt factor of oscillation stop detection, watchdog timer interrupt or voltage detection interrupt) generated interrupt factor bit showing interrupt factor oscillation stop detection (a) the ocd3 bit in the ocd register = 1 ( (a) or (b) ) (b) the ocd1 to ocd0 bits in the ocd register = 11 2 and the ocd2 bit = 1 watchdog timer the d43 bit in the d4int register = 1 voltage detection the d42 bit in the d4int register = 1 6.5 oscillation stop detection function
r8c/11 group rev.1.20 jan 27, 2006 page 44 of 204 rej09b0062-0120 7. protection in the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. figure 7.1 shows the prcr register. the following lists the registers protected by the prcr register. registers protected by prc0 bit: cm0, cm1, and ocd, hr0, hr1 registers registers protected by prc1 bit: pm0 and pm1 registers registers protected by prc2 bit: pd0 register registers protected by prc3 bit: vcr2 and d4int registers set the prc2 bit to 1 (write enabled) and then write to any address, and the prc2 bit will be set to 0 (write protected). the registers protected by the prc2 bit should be changed in the next instruction after setting the prc2 bit to 1 . make sure no interrupts will occur between the instruction in which the prc2 bit is set to 1 and the next instruction. the prc0, prc1 and prc3 bits are not automatically set to 0 by writing to any address. they can only be set to 0 in a program. figure 7.1 prcr register 7. protection p r o t e c t r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t p r c r0 0 0 a 1 6 0 0 x x x 0 0 0 2 bit name b i t s y m b o l b 7 b 6b 5b 4b 3 b 2b 1b 0 0 : write protected 1 : write enabled p r c 1 p r c 0 function r w n o t e s : 1 . t h e p r c 2 b i t i s s e t t o 0 b y w r i t i n g t o a n y a d d r e s s a f t e r s e t t i n g i t t o 1 . o t h e r b i t s a r e n o t s e t t o 0 b y w r i t i n g t o a n y a d d r e s s , a n d m u s t t h e r e f o r e b e s e t t o 0 i n a p r o g r a m . r w r w protect bit 0 protect bit 1 p r o t e c t b i t 2 enable write to cm0, cm1, ocd, hr0, hr1 registers 0 : write protected 1 : write enabled enable write to pm0, pm1 registers 0 : w r i t e p r o t e c t e d 1 : w r i t e e n a b l e d 1 e n a b l e w r i t e t o p d 0 r e g i s t e r 0 0 r w when read, its content is 0 . (b7-b6) r e s e r v e d b i t when write, should set to 0 ( b 5 - b 4 ) r e s e r v e d b i t ro p r c 2 r w p r o t e c t b i t 3 0 : w r i t e p r o t e c t e d 1 : w r i t e e n a b l e d e n a b l e w r i t e t o v c r 2 , d 4 i n t r e g i s t e r s p r c 3 r w
r8c/11 group 8. processor mode rev.1.20 jan 27, 2006 page 45 of 204 rej09b0062-0120 8. processor mode 8.1 types of processor mode the processor mode is single-chip mode. table 8.1 shows the features of the processor mode. figure 8.1 shows the pm0 and pm1 register. p r o c e s s o r m o d e r e g i s t e r 0 (1 ) symbol address after reset pm0 0004 16 00 16 b i t n a m e function b i t s y m b o l r w b 7b6b 5b 4 b 3b2b 1b0 p m 0 3 ( b 2 - b 0 ) reserved bit s o f t w a r e r e s e t b i t s e t t i n g t h i s b i t t o 1 r e s e t s t h e m i c r o c o m p u t e r . w h e n r e a d , i t s c o n t e n t i s 0 . r w r w m u s t s e t t o 0 n o t e s : 1 . s e t t h e p r c 1 b i t i n t h e p r c r r e g i s t e r t o " 1 " ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r . 00 n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s " 0 " . ( b 7 - b 4 ) 0 figure 8.1 pm0 register and pm1 register table 8.1 features of processor mode p r o c e s s o r m o d e r e g i s t e r 1 (1 ) s y m b o la d d r e s sa f t e r r e s e t p m 10 0 0 5 1 6 0 0 1 6 b i t n a m e function b i t s y m b o l r w b7 b 6b 5b 4 b 3b 2b 1b 0 r w n o t e s : 1 . s e t t h e p r c 1 b i t i n t h e p r c r r e g i s t e r t o " 1 " ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 . p m 1 2 b i t i s s e t t o 1 b y w r i t i n g a 1 i n a p r o g r a m . ( w r i t i n g a 0 h a s n o e f f e c t . ) 0 : w a t c h d o g t i m e r i n t e r r u p t 1 : w a t c h d o g t i m e r r e s e t (2 ) w d t i n t e r r u p t / r e s e t s w i t c h b i t pm12 r w 0 0 s e t t o 0 ( b 1 - b 0 ) r e s e r v e d b i t nothing is assigned. when write, set to 0 . when read, its content is "0". ( b 6 - b 3 ) 0 r w s e t t o 0 (b7) r e s e r v e d b i t processor mode access space pins which are assigned i/o ports single-chip mode sfr, internal ram, internal rom all pins are i/o ports or peripheral function i/o pins
9. bus r8c/11 group rev.1.20 jan 27, 2006 page 46 of 204 rej09b0062-0120 9. bus during access, the rom/ram and the sfr have different bus cycles. table 9.1 shows bus cycles for access space. the rom/ram and sfr are connected to the cpu through an 8-bit bus. when accessing in word (16 bits) units, these spaces are accessed twice in 8-bit units. table 9.2 shows bus cycles in each access space. space even address byte access cpu clock data address sfr, data flash program rom/ram even odd data data data data data data data data data data data odd odd odd+1 odd odd+1 even even even+1 even+1 data address data address data address data address data address data address data address odd address byte access even address word access odd address word access data even cpu clock cpu clock cpu clock cpu clock cpu clock cpu clock cpu clock table 9.1 bus cycles for access space access space bus cycle sfr/data flash 2 cpu clock cycles program rom/ram 1 cpu clock cycles table 9.2 access unit and bus operation
r8c/11 group rev.1.20 jan 27, 2006 page 47 of 204 rej09b0062-0120 maskable interrupt: an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. non-maskable interrupt: an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 10.1 interrupts interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10. interrupt 10.1 interrupt overview 10.1.1 type of interrupts figure 10.1 shows types of interrupts. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 48 of 204 rej09b0062-0120 10.1.2 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non- maskable interrupts. undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. overflow interrupt an overflow interrupt occurs when executing the into instruction with the o flag set to 1 (the operation resulted in an overflow). the following are instructions whose o flag changes by arith- metic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub brk interrupt a brk interrupt occurs when executing the brk instruction. int instruction interrupt an int instruction interrupt occurs when executing the int instruction. software interrupt numbers 0 to 63 can be specified for the int instruction. because software interrupt numbers 4 to 31 are as- signed to peripheral function interrupts, the same interrupt routine as for peripheral function inter- rupts can be executed by executing the int instruction. in software interrupt numbers 0 to 31, the u flag is saved to the stack during instruction execution and is cleared to 0 (isp selected) before executing an interrupt sequence. the u flag is restored from the stack when returning from the interrupt routine. in software interrupt numbers 32 to 63, the u flag does not change state during instruction execution, and the sp then selected is used. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 49 of 204 rej09b0062-0120 10.1.3 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral function inter- rupts. (1) special interrupts special interrupts are non-maskable interrupts. watchdog timer interrupt generated by the watchdog timer. once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. for details about the watchdog timer, refer to chapter 11, watchdog timer. oscillation stop detection interrupt generated by the oscillation stop detection function. for details about the oscillation stop detection function, refer to chapter 6, clock generation circuit. voltage detection interrupt generated by the voltage detection circuit. for details about the voltage detection circuit, refer to section 5.4, voltage detection circuit. single-step interrupt do not normally use this interrupt because it is provided exclusively for use by development support tools. address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indicated by the rmad0 to rmad1 register that corresponds to one of the aier register's aier0 or aier1 bit which is "1" (address match interrupt enabled). for details about the address match inter- rupt, refer to section 10.4, address match interrupt. (2) peripheral function interrupts peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal functions. the interrupt factors for peripheral function interrupts are listed in table 10.2. relocatable vector tables . for details about the peripheral functions, refer to the description of each peripheral function in this manual. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 50 of 204 rej09b0062-0120 interrupt factor vector addresses remarks reference address (l) to address (h) undefined instruction 0ffdc 16 to 0ffdf 16 interrupt on und instruction r8c/tiny series overflow 0ffe0 16 to 0ffe3 16 interrupt on into instruction software manual brk instruction 0ffe4 16 to 0ffe7 16 address match 0ffe8 16 to 0ffeb 16 18.1 address match interrupt single step (1) 0ffec 16 to 0ffef 16 watchdog timer 0fff0 16 to 0fff3 16 11. watchdog timer oscillation stop 6. clock generation detection circuit voltage detection 5.4 voltage detection circuit (reserved) 0fff4 16 to 0fff7 16 (reserved) 0fff8 16 to 0fffb 16 reset 0fffc 16 to 0ffff 16 5. reset notes: 1. do not normally use this interrupt because it is provided exclusively for use by development sup- port tools. figure 10.2 interrupt vector aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa 0 0 0 0 high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address (l) lsb msb vector address (h) 10.1.4 interrupts and interrupt vector one interrupt vector consists of 4 bytes. set the start address of each interrupt routine in the respec- tive interrupt vectors. when an interrupt request is accepted, the cpu branches to the address set in the corresponding interrupt vector. figure 10.2 shows the interrupt vector. fixed vector tables the fixed vector tables are allocated to the addresses from 0ffdc 16 to 0ffff 16 . table 10.1 lists the fixed vector tables. in the flash memory version of microcomputer, the vector addresses (h) of fixed vectors are used by the id code check function. for details, refer to section 17.3, functions to prevent flash memory from rewriting. table 10.1 fixed vector tables if the contents of address 0ffe7 16 is ff 16 , program ex- ecution starts from the address shown by the vector in the relocatable vector table. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 51 of 204 rej09b0062-0120 table 10.2 vector tables software interrupt number reference v e c t o r a d d r e s s (1 ) a d d r e s s ( l ) t o a d d r e s s ( h ) 0 1 t o 1 2 i n t e r r u p t f a c t o r b r k i n s t r u c t i o n (2 ) r 8 c / t i n y s e r i e s s o f t w a r e m a n u a l (reserved) + 0 t o + 3 ( 0 0 0 0 1 6 t o 0 0 0 3 1 6 ) + 5 2 t o + 5 5 ( 0 0 3 4 1 6 t o 0 0 3 7 1 6 ) + 5 6 t o + 5 9 ( 0 0 3 8 1 6 t o 0 0 3 b 1 6 ) 13 14 1 5 k e y i n p u t a / d c o n v e r s i o n 1 0 . 3 k e y i n p u t i n t e r r u p t 1 4 . a / d c o n v e r t e r ( r e s e r v e d ) notes: 1. address relative to address in intb. 2. these interru p ts cannot be disabled usin g the i fla g . + 6 8 t o + 7 1 ( 0 0 4 4 1 6 t o 0 0 4 7 1 6 ) +72 to +75 (0048 16 to 004b 16 ) + 7 6 t o + 7 9 ( 0 0 4 c 1 6 t o 0 0 4 f 1 6 ) + 8 0 t o + 8 3 ( 0 0 5 0 1 6 t o 0 0 5 3 1 6 ) +84 to +87 (0054 16 to 0057 16 ) +88 to +91 (0058 16 to 005b 16 ) +92 to +95 (005c 16 to 005f 16 ) + 9 6 t o + 9 9 ( 0 0 6 0 1 6 t o 0 0 6 3 1 6 ) + 1 0 0 t o + 1 0 3 ( 0 0 6 4 1 6 t o 0 0 6 7 1 6 ) + 1 0 4 t o + 1 0 7 ( 0 0 6 8 1 6 t o 0 0 6 b 1 6 ) +108 to +111 (006c 16 to 006f 16 ) +116 to +119 (0074 16 to 0077 16 ) + 1 2 8 t o + 1 3 1 ( 0 0 8 0 1 6 t o 0 0 8 3 1 6 ) + 2 5 2 t o + 2 5 5 ( 0 0 f c 1 6 t o 0 0 f f 1 6 ) to 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 63 to uart0 transmit u a r t 0 r e c e i v e u a r t 1 t r a n s m i t uart1 receive timer x timer y timer z t i m e r c int1 i n t 3 i n t 2 s o f t w a r e i n t e r r u p t (2 ) 1 3 . s e r i a l i n t e r f a c e 1 0 . 2 . 1 i n t 0 i n t e r r u p t int0 (reserved) (reserved) 10.2.3 int2 interrupt 1 2 . 1 t i m e r x 12.2 timer y 12.3 timer z 1 2 . 4 t i m e r c 10.2.3 int1 interrupt r 8 c / t i n y s e r i e s s o f t w a r e m a n u a l +64 to +67 (0040 16 to 0043 16 ) 16 c o m p a r e 1 1 2 . 4 t i m e r c + 1 1 2 t o + 1 1 5 ( 0 0 7 0 1 6 t o 0 0 7 3 1 6 ) c o m p a r e 0 1 2 . 4 t i m e r c 1 0 . 2 . 4 i n t 3 i n t e r r u p t relocatable vector tables the 256 bytes beginning with the start address set in the intb register comprise a reloacatable vector table area. table 10.2 lists interrupts and vector tables located in the relocatable vector table. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 52 of 204 rej09b0062-0120 10.1.5 interrupt control the following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. what is explained here does not apply to nonmaskable interrupts. use the flg register s i flag, ipl, and each interrupt control register's ilvl2 to ilvl0 bits to enable/ disable the maskable interrupts. whether an interrupt is requested is indicated by the ir bit in each interrupt control register. figure 10.3 shows the interrupt control registers. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 53 of 204 rej09b0062-0120 figure 10.3 interrupt control registers symbol address after reset int0ic 005d 16 xx00x000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ilvl0 ir pol i n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t i n t e r r u p t r e q u e s t b i t polarity select bit (3, 4) reserved bit 0 : i n t e r r u p t n o t r e q u e s t e d 1 : i n t e r r u p t r e q u e s t e d 0 : selects falling edge 1 : selects rising edge set to 0 i l v l 1 i l v l 2 notes: 1. only "0" can be written to the ir bit. (do not write "1"). 2. to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. refer to the paragraph 19.2.6 changing interrupt control registers . 3. if the intopl bit in the inten register is set to 1 (both edges), set the pol bit to "0 " (selecting falling edge). 4. the ir bit may be set to 1 (interrupt requested) when the pol bit is rewritten. refer to the paragraph 19.2.5 changing interrupt factor . i n t e r r u p t c o n t r o l r e g i s t e r ( 2 ) b 7b 6b 5b 4b 3b 2b 1b 0 bit name f u n c t i o n b i t s y m b o l r w s y m b o la d d r e s sa f t e r r e s e t k u p i c0 0 4 d 1 6 x x x x x 0 0 0 2 a d i c0 0 4 e 1 6 x x x x x 0 0 0 2 c m p 1 i c0 0 5 0 1 6 x x x x x 0 0 0 2 s 0 t i c , s 1 t i c0 0 5 1 1 6 , 0 0 5 3 1 6 x x x x x 0 0 0 2 s 0 r i c , s 1 r i c0 0 5 2 1 6 , 0 0 5 4 1 6 x x x x x 0 0 0 2 i n t 2 i c0 0 5 5 1 6 x x x x x 0 0 0 2 t x i c0 0 5 6 1 6 x x x x x 0 0 0 2 t y i c0 0 5 7 1 6 x x x x x 0 0 0 2 t z i c0 0 5 8 1 6 x x x x x 0 0 0 2 i n t 1 i c0 0 5 9 1 6 x x x x x 0 0 0 2 i n t 3 i c0 0 5 a 1 6 x x x x x 0 0 0 2 t c i c0 0 5 b 1 6 x x x x x 0 0 0 2 c m p 0 i c0 0 5 c 1 6 x x x x x 0 0 0 2 i l v l 0 i r i n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t i n t e r r u p t r e q u e s t b i t 0 : i n t e r r u p t n o t r e q u e s t e d 1 : i n t e r r u p t r e q u e s t e d i l v l 1 i l v l 2 nothing is assigned. when write, set to 0 . when read, its content is indeterminate. 0 0 0 : l e v e l 0 ( i n t e r r u p t d i s a b l e d ) 0 0 1 : l e v e l 1 0 1 0 : l e v e l 2 0 1 1 : l e v e l 3 1 0 0 : l e v e l 4 1 0 1 : l e v e l 5 1 1 0 : l e v e l 6 1 1 1 : l e v e l 7 b2 b1 b0 0 0 0 : l e v e l 0 ( i n t e r r u p t d i s a b l e d ) 0 0 1 : l e v e l 1 0 1 0 : l e v e l 2 0 1 1 : l e v e l 3 1 0 0 : l e v e l 4 1 0 1 : l e v e l 5 1 1 0 : l e v e l 6 1 1 1 : l e v e l 7 b2 b1 b0 0 r w r w r w rw (1) ( b 7 - b 4 ) rw rw rw r w rw r w (1 ) rw ( b 7 - b 6 ) n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e . ( b 5 ) 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 54 of 204 rej09b0062-0120 i flag the i flag enables or disables the maskable interrupt. setting the i flag to 1 (enabled) enables the maskable interrupt. setting the i flag to 0 (disabled) disables all maskable interrupts. ir bit the ir bit is set to 1 (interrupt requested) when an interrupt request is generated. then, when the interrupt request is accepted and the cpu branches to the corresponding interrupt vector, the ir bit is cleared to 0 (= interrupt not requested). the ir bit can be cleared to 0 in a program. note that do not write 1 to this bit. table 10.4 interrupt priority levels enabled by ipl table 10.3 settings of interrupt priority levels ilvl2 to ilvl0 bits interrupt priority level priority order 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 lowest highest enabled interrupt priority levels interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 ilvl2 to ilvl0 bits and ipl interrupt priority levels can be set using the ilvl2 to ilvl0 bits. table 10.3 shows the settings of interrupt priority levels and table 10.4 shows the interrupt priority levels enabled by the ipl. the following are conditions under which an interrupt is accepted: i flag = 1 ir bit = 1 interrupt priority level > ipl the i flag, ir bit, ilvl2 to ilvl0 bits and ipl are independent of each other. in no case do they affect one another. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 55 of 204 rej09b0062-0120 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. the cpu behavior during the interrupt sequence is described below. figure 10.4 shows time re- quired for executing the interrupt sequence. (1) the cpu gets interrupt information (interrupt number and interrupt request priority level) by read- ing the address 00000 16 . then it clears the ir bit for the corresponding interrupt to 0 (interrupt not requested). (2) the flg register immediately before entering the interrupt sequence is saved to the cpu internal temporary register (1) . (3) the i, d and u flags in the flg register become as follows: the i flag is cleared to 0 (interrupts disabled). the d flag is cleared to 0 (single-step interrupt disabled). the u flag is cleared to 0 (isp selected). however, the u flag does not change state if an int instruction for software interrupt numbers 32 to 63 is executed. (4) the cpu s internal temporary register (1) is saved to the stack. (5) the pc is saved to the stack. (6) the interrupt priority level of the accepted interrupt is set in the ipl. (7) the start address of the relevant interrupt routine set in the interrupt vector is stored in the pc. after the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. notes: 1. this register cannot be used by user. indeterminate indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 16 indeterminate sp-2 sp-4 vec vec+2 pc cpu clock address bus data bus wr the indeterminate state depends on the instruction queue buffer. a read cycle occurs when the instruction queue buffer is ready to accept instructions. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 rd vec+1 contents sp-3 contents sp-1 sp-3 vec+1 sp-1 contents figure 10.4 time required for executing interrupt sequence 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 56 of 204 rej09b0062-0120 interrupt factor 7 level that is set to ipl watchdog timer, oscillation stop detection, voltage detection software, address match, single-step not changed variation of ipl when interrupt request is accepted when a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. when a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in table 10.5 is set in the ipl. shown in table 10.5 are the ipl values of software and special interrupts when they are accepted. table 10.5 ipl level that is set to ipl when a software or special interrupt is accepted figure 10.5 interrupt response time interrupt response time figure 10.5 shows the interrupt response time. the interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the inter- rupt routine is executed. specifically, it consists of a time from when an interrupt request is gener- ated till when the instruction then executing is completed (see #a in figure 10.5) and a time during which the interrupt sequence is executed (20 cycles, see #b in figure 10.5). instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) 20 cycles (b) interrupt request acknowledged interrupt request generated (a) a time from when an interrupt request is generated till when the instruction then executing is completed. the length of this time varies with the instruction being executed. the divx instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) 21 cycles for address match and single-step interrupts. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 57 of 204 rej09b0062-0120 ?saving registers in the interrupt sequence, the flg register and pc are saved to the stack. at this time, the 4 high-order bits in the pc and the 4 high-order (ipl) and 8 low-order bits in the flg register, 16 bits in total, are saved to the stack first. next, the 16 low-order bits in the pc are saved. figure 10.6 shows the stack status before and after an interrupt request is accepted. the other necessary registers must be saved in a program at the beginning of the interrupt routine. the pushm instruction can save several registers in the register bank being currently used (1) with a single instruction. notes: 1. selectable from registers r0, r1, r2, r3, a0, a1, sb, and fb. address content of previous stack stack [sp] spvalue before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flg l content of previous stack stack flg h pc h [sp] new sp value content of previous stack m + 1 msb lsb pc l pc m figure 10.6 stack status before and after acceptance of interrupt request figure 10.7 operation of saving register [ s p ] [ s p ] 1 [ s p ] 2 [ s p ] 3 [ s p ] 4 [ s p ] 5 a d d r e s s s e q u e n c e i n w h i c h o r d e r r e g i s t e r s a r e s a v e d ( 2 ) ( 1 ) f i n i s h e d s a v i n g r e g i s t e r s i n f o u r o p e r a t i o n s . ( 3 ) ( 4 ) n o t e s : 1 .[ s p ] d e n o t e s t h e i n i t i a l v a l u e o f t h e s p w h e n i n t e r r u p t r e q u e s t i s a c k n o w l e d g e d . a f t e r r e g i s t e r s a r e s a v e d , t h e s p c o n t e n t i s [ s p ] m i n u s 4 . p c m s t a c k f l g l p c l s a v e d , 8 b i t s a t a t i m e f l g h p c h the registers are saved in four steps, 8 bits at a time. figure 10.7 shows the operation of the saving registers. notes: 1. when any int instruction in software numbers 32 to 63 has been executed, this is the sp indi- cated by the u flag. otherwise, it is the isp. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 58 of 204 rej09b0062-0120 interrupt priority if two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. for maskable interrupts (peripheral functions), any desired priority level can be selected using the ilvl2 to ilvl0 bits. however, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. the watchdog timer and other special interrupts have their priority levels set in hardware. figure 10.8 shows the hardware interrupt priority. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. returning from an interrupt routine the flg register and pc in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the reit instruction at the end of the interrupt routine. thereafter the cpu returns to the program which was being executed before accepting the interrupt request. return the other registers saved by a program within the interrupt routine using the popm or similar instruction before executing the reit instruction. figure 10.8 hardware interrupt priority reset > wdt/oscillation stop detection/voltage detection > peripheral function > single step > address match 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 59 of 204 rej09b0062-0120 figure 10.9 interrupts priority select circuit interrupt request acce p ted lowest p r i o r i t y o f p e r i p h e r a l f u n c t i o n i n t e r r u p t s ( i f p r i o r i t y l e v e l s a r e s a m e ) interrupt request level resolution output signal a/d conversion u a r t 1 t r a n s m i s s i o n u a r t 0 t r a n s m i s s i o n key inpu t i p l i flag i n t 2 a d d r e s s m a t c h w a t c h d o g t i m e r o s c i l l a t i o n s t o p d e t e c t i o n v o l t a g e d e t e c t i o n h i g h e s t p r i o r i t y l e v e l o f e a c h i n t e r r u p t l e v e l 0 ( d e f a u l t v a l u e ) timer z t i m e r x timer c timer y uart1 reception u a r t 0 r e c e p t i o n i n t 3 i n t 1 int0 compare 0 compare 1 interrupt priority resolution circuit the interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. figure 10.9 shows the interrupts priority select circuit. 10.1 interrupt overview
r8c/11 group rev.1.20 jan 27, 2006 page 60 of 204 rej09b0062-0120 ______ 10.2 int interrupt ________ 10.2.1 int0 interrupt _______ int0 interrupt is triggered by an int0 input. when using int0 interrupts, the int0en bit in the inten register must be set to 1 (enabling). the edge polarity is selected using the int0pl bit in the inten register and the pol bit in the int0ic register. inputs can be passed through a digital filter with three different sampling clocks. _______ the int0 pin is shared with the external trigger input pin of timer z. figure 10.10 shows the inten and int0f registers. figure 10.10 inten register and int0f register e x t e r n a l i n p u t e n a b l e r e g i s t e r bit name f u n c t i o n bit symbol r w s y m b o la d d r e s sa f t e r r e s e t i n t e n 0 0 9 6 1 6 0 0 1 6 i n t 0 e n b 7b 6b 5b4b 3b 2b 1b 0 i n t 0 i n p u t e n a b l e b i t (1 ) 0 : d i s a b l e d 1 : e n a b l e d 0 : o n e e d g e 1 : b o t h e d g e s set to 0 i n t 0 i n p u t p o l a r i t y s e l e c t b i t (2 ) reserved bit i n t 0 p l ( b 7 - b 2 ) notes: 1. this bit must be set while the int0stg bit in the pum register is set to 0 (one-shot trigger disabled). 2. when setting the int0pl bit to 1 (selecting both edges), the pol bit in the int0ic must be set to 0 (selecting falling edge). 3. the ir bit in the int0ic register may be set to 1 (interrupt requested) when the int0pl bit is rewritten. refer to the paragraph 19.2.5 changing interrupt factor in the usage notes reference book. i n t 0 i n p u t f i l t e r s e l e c t r e g i s t e r bit name f u n c t i o n b i t s y m b o l s y m b o la d d r e s sa f t e r r e s e t i n t 0 f 0 0 1 e 1 6 x x x x x 0 0 0 2 int0f0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 : n o f i l t e r 0 1 : f i l t e r w i t h f 1 s a m p l i n g 1 0 : f i l t e r w i t h f 8 s a m p l i n g 1 1 : f i l t e r w i t h f 3 2 s a m p l i n g set to 0 reserved bit i n t 0 f 1 b 1 b 0 int0 input filter select bit nothing is assigned. when write, set to 0 . if read, it content is indeterminate. r w r w rw rw rw r w rw (b2) ( b 7 - b 3 ) 0 0000 00 ______ 10.2 int interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 61 of 204 rej09b0062-0120 _______ 10.2.2 int0 input filter _______ the int0 input has a digital filter which can be sampled by one of three sampling clocks. the sampling clock is selected using the int0f1 to int0f0 bits in the int0f register. the ir bit in the int0ic register is set to 1 (interrupt requested) when the sampled input level matches three times. when the int0f1 to int0f0 bits are set to 01 2 , 10 2 , or 11 2 , the p4_5 bit in the p4 register indicates the filtered value. _____ figure 10.11 shows the int0 input filter configuration. figure 10.12 shows an operation example of _____ int0 input filter. ______ figure 10.11 int0 input filter digital filter (input level matches 3x) port p45 direction register f 1 f 8 f 32 int0 int0 interrupt int0en int0f1 to int0f0 =01 2 =10 2 =11 2 int0f1 to int0f0 =00 2 =00 2 p4_5 bit other than sampling clock int0f0, int0f1: bits in int0f register int0en: bit in inten register ______ figure 10.12 operation example of int0 input filter p45 input sampling timing p4_5 in p4 register ir bit in int0ic register set to 0 in program this is an operation example when the int0f1 to int0f0 bits in the int0f register is set to 01 2 , 10 2 , or 11 2 (passing digital filter). ______ 10.2 int interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 62 of 204 rej09b0062-0120 ______ ______ 10.2.3 int1 interrupt and int2 interrupt ______ ______ int1 interrupts are triggered by int1 inputs. the edge polarity is selected with the r0edg bit in the ______ txmr register. the int1 pin is shared with the cntr0 pin. ______ ______ int2 interrupts are triggered by int2 inputs. the edge polarity is selected with the r1edg bit in the ______ tyzmr register. the int2 pin is shared with the cntr1 pin. ______ _____ figure 10.13 shows the txmr and tyzmr registers when using int1 and int2 interrupts. ______ ______ figure 10.13 txmr register and tyzmr register when int1 and int2 interrupt used t i m e r x m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t x m r0 0 8 b 1 6 0 0 1 6 b i t n a m e function b i t s y m b o l r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : t i m e r m o d e o r p u l s e p e r i o d m e a s u r e m e n t m o d e (3 ) b1 b0 txmod2 t x s t x m o d 1 r0edg t x m o d 0 txocnt o p e r a t i o n m o d e s e l e c t b i t 0 , 1 t i m e r x c o u n t s t a r t f l a g 0 : stops counting 1 : starts counting o p e r a t i o n m o d e s e l e c t b i t 2 00 0 m u s t s e t t o " 0 " i n t i m e r m o d e 0 : rising edge 1 : falling edge 0 txedg t x u n d r w r w rw rw rw rw rw rw i n t 1 / c n t r 0 p o l a r i t y s w i t c h i n g b i t (1 , 2 ) must set to "0" in timer mode must set to "0" in timer mode 0 : o t h e r t h a n p u l s e p e r i o d m e a s u r e m e n t m o d e (3 ) n o t e s : 1 . t h e i r b i t i n t h e i n t 1 i c m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 2 . t h i s b i t i s u s e d t o s e l e c t t h e p o l a r i t y o f i n t 1 i n t e r r u p t i n t i m e r m o d e . 3 . w h e n u s i n g i n t 1 i n t e r r u p t s , s h o u l d s e l e c t t i m e r m o d e . 00 t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 bit name f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t z m o d 1 tys t y w c t y m o d 0 t z m o d 0 timer y operation mode bit timer y write control bit 0 : t i m e r m o d e (1 ) t z w c t z s 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g timer z-related bit timer y count start flag 0 r w r w rw r w rw rw r 1 e d g 0 : r i s i n g e d g e 1 : f a l l i n g e d g e i n t 2 / c n t r 1 p o l a r i t y s w i t c h i n g b i t (2 ) r w r w r w n o t e s : 1 . w h e n u s i n g i n t 2 i n t e r r u p t s , m u s t s e t t o t i m e r m o d e . 2 . t h e i r b i t i n t h e i n t 2 i c m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 1 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . function varies depending on the operation mode ______ 10.2 int interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 63 of 204 rej09b0062-0120 ______ 10.2.4 int3 interrupt _____ ______ int3 interrupts are triggered by int3 inputs. the tcc07 bit in the tcc0 register should be se to 0 ______ _______ (int3). the int3 input has a digital filter which can be sampled by one of three sampling clocks. the sampling clock is selected using the tcc11 to tcc10 bits in the tcc1 register. the ir bit in the int3ic register is set to 1 (interrupt requested) when the sampled input level matches three times. the p3_3 bit in the p3 register indicates the previous value before filtering regardless of values set in the tcc11 to tcc10 bits. _______ the int3 pin is shared with the tc in pin. _____ when setting the tcc07 bit to 1 (f ring128 ), int3 interrupts are triggered by f ring128 clock. the ir bit in the int3ic register is set to 1 (interrupt requested) every f ring128 clock cycle or every half f ring128 clock cycle. figure 10.14 shows the tcc0 and tcc1 registers. ______ 10.2 int interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 64 of 204 rej09b0062-0120 t i m e r c c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sa f t e r r e s e t t c c 00 0 9 a 1 6 0 0 1 6 b i t n a m e f u n c t i o n bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f r i n g - f a s t t c c 0 4 t c c 0 2 t c c 0 1 t c c 0 0 t c c 0 3 timer c control bit timer c count source select bit (1) 0 : c o u n t s t o p 1 : c o u n t s t a r t tcc07 b 2 b 1 0 0 : rising edge 0 1 : falling edge 1 0 : both edges 1 1 : avoid this setting b4 b3 r w ( b 6 - b 5 ) int3 interrupt and capture polarity select bit (1, 2) i n t 3 i n t e r r u p t / c a p t u r e i n p u t s w i t c h i n g b i t (1 , 2 ) 0 : i n t 3 1 : f r i n g 1 2 8 r w r w r w r w notes: 1. change this bit when tcc00 bit is set to 0 (count stop). 2. the ir bit in the int3ic may be set to 1 (interrupt requested) when the tcc03, tcc04, or tcc07 bit is rewritten. refer to the paragraph 19.2.5 changing interrupt factor in the usage notes reference book. r w r w r e s e r v e d b i t m u s t s e t t o " 0 " r w 0 0 figure 10.14 tcc0 register and tcc1 register t i m e r c c o n t r o l r e g i s t e r 1 s y m b o la d d r e s sa f t e r r e s e t t c c 10 0 9 b 1 6 0 0 1 6 bit name function b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t c c 1 1 t c c 1 0 b1 b0 int3 input filter select bit (1) timer c counter reload select bit (2, 3) t c c 1 2 r w r w r w r w 0 0 : n o f i l t e r 0 1 : f i l t e r w i t h f 1 s a m p l i n g 1 0 : f i l t e r w i t h f 8 s a m p l i n g 1 1 : f i l t e r w i t h f 3 2 s a m p l i n g 0: no reload (free-run) 1: set tc register to 0000 16 at compare 1 match compare 0/capture select bit t c c 1 3 r w 0: capture (input capture mode) (2) 1: compare 0 output (output compare mode) c o m p a r e 0 o u t p u t m o d e s e l e c t b i t (3 ) t c c 1 4 r w 0 0: cmp output remains unchanged even when compare 0 matched 0 1: cmp output is reversed when compare 0 signal is matched 1 0: cmp output is set to low when compare 0 signal is matched 1 1: cmp output is set to high when compare 0 signal is matched b 5 b 4 compare 1 output mode select bit (3) tcc16 r w 0 0: cmp output remains unchanged even when compare 1 matched 0 1: cmp output is reversed when compare 1 signal is matched 1 0: cmp output is set to low when compare 1 signal is matched 1 1: cmp output is set to high when compare 1 signal is matched b7 b6 tcc15 tcc17 n o t e s : 1 . i n p u t i s r e c o g n i z e d o n l y w h e n t h e s a m e v a l u e f r o m i n t 3 p i n i s s a m p l e d t h r e e t i m e s i n s u c c e s s i o n . 2 . m o d i f y t h e t c c 1 3 b i t w h e n t h e t c c 0 0 b i t i n t h e t c c 0 r e g i s t e r i s s e t t o 0 ( c o u n t s t o p s ) 3 . s e t t h e t c c 1 2 , t c c 1 4 t o t c c 1 7 b i t s t o 0 w h e n t h e t c c 1 3 b i t i s s e t t o 0 ( i n p u t c a p t u r e m o d e ) . ______ 10.2 int interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 65 of 204 rej09b0062-0120 key input interrupt request pull-up transistor pull-up transistor pull-up transistor ki 3 ki 2 pu02 bit in pur0 register pd1_3 bit in pd1 register ki 1 ki 0 pd1_3 bit ki3en bit pd1_2 bit ki2en bit pd1_1 bit ki1en bit pd1_0 bit ki0en bit ki3pl=1 ki3pl=0 ki2pl=1 ki2pl=0 ki1pl=1 ki1pl=0 ki0pl=1 ki0pl=0 kupic register interrupt control circuit pull-up transistor ki0en, ki1en, ki2en, ki3en, ki0pl, ki1pl, ki2pl, ki3pl: bits in kien register pd1_0, pd1_1, pd1_2, pd1_3: bits in pd1 register figure 10.15 key input interrupt 10.3 key input interrupt _____ _____ a key input interrupt is generated on an input edge of any of the k1 0 to k1 3 pins. key input interrupts can _____ be used as a key-on wakeup function to exit wait or stop mode. kii input can be enabled or disabled selecting with the kiien (i=0 to 3) bit in the kien register. the edge polarity can be rising edge or falling _____ edge selecting with the kiipl bit in the kien register. note, however, that while input on any kii pin which has had the kiipl bit set to 0 (falling edge) is pulled low, inputs on all other pins of the port are not _____ detected as interrupts. similarly, while input on any kii pin which has had the kiipl bit set to 1 (rising edge) is pulled high, inputs on all other pins of the port are not detected as interrupts. figure 10.15 shows a block diagram of the key input interrupt. figure 10.16 kien register k e y i n p u t e n a b l e r e g i s t e r bit name function b i t s y m b o l r w s y m b o la d d r e s sa f t e r r e s e t k i e n 0 0 9 8 1 6 0 0 1 6 ki0en b 7b 6b 5b 4b 3b 2b 1b 0 k i 0 i n p u t e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d 0 : f a l l i n g e d g e 1 : r i s i n g e d g e s 0 : d i s a b l e d 1 : e n a b l e d 0 : f a l l i n g e d g e 1 : r i s i n g e d g e s 0 : d i s a b l e d 1 : e n a b l e d k i 0 i n p u t p o l a r i t y s e l e c t b i t k i 1 i n p u t e n a b l e b i t k i 1 i n p u t p o l a r i t y s e l e c t b i t k i 2 i n p u t e n a b l e b i t ki2 input polarity select bit 0 : falling edge 1 : rising edges ki0pl ki1en ki1pl ki2en ki2pl k i 3 i n p u t e n a b l e b i t0 : d i s a b l e d 1 : e n a b l e d ki3en k i 3 i n p u t p o l a r i t y s e l e c t b i t0 : f a l l i n g e d g e 1 : r i s i n g e d g e s ki3pl r w r w r w r w rw r w r w r w n o t e s : 1 . t h e i r b i t i n t h e k u p i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e k i e n r e g i s t e r i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 10.3 key input interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 66 of 204 rej09b0062-0120 10.4 address match interrupt an address match interrupt is generated immediately before executing the instruction at the address indicated by the rmadi register (i=0, 1). set the start address of any instruction in the rmadi register. use the aier0 and aier1 bits in the aier register to enable or disable the interrupt. note that the address match interrupt is unaffected by the i flag and ipl. the value of the pc that is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the rmad i register (see the paragraph register saving for the value of the pc). not appropriate return address is pushed on the stack. there are two ways to return from the address match interrupt as follows: change the content of the stack and use a reit instruction. use an instruction such as pop to restore the stack as it was before an interrupt request was acknowl- edged. and then use a jump instruction. table 10.6 lists the value of the pc that is saved to the stack when an address match interrupt is acknowl- edged. figure 10.17 shows the aier, and rmad1 to rmad0 registers. table 10.6 value of pc saved to stack when address match interrupt acknowledged address indicated by rmadi register (i=0,1) pc value saved (1) 16-bit operation code instruction address indicated by instruction shown below among 8-bit operation code instructions rmadi register + 2 add.b:s #imm8,dest sub.b:s #imm8,dest and.b:s #imm8,dest or.b:s #imm8,dest mov.b:s #imm8,dest stz.b:s #imm8,dest stnz.b:s #imm8,dest stzx.b:s #imm81,#imm82,dest cmp.b:s #imm8,dest pushm src popm dest jmps #imm8 jsrs #imm8 mov.b:s #imm,dest (however, dest = a0 or a1) instructions other than the above address indicated by rmadi register + 1 notes: 1. see the paragraph saving registers for the pc value saved. table 10.7 relationship between address match interrupt factors and associated registers address match interrupt factors address match interrupt enable bit address match interrupt register address match interrupt 0 aier0 rmad0 address match interrupt 1 aier1 rmad1 10.4 address match interrupt
r8c/11 group rev.1.20 jan 27, 2006 page 67 of 204 rej09b0062-0120 bit name bit symbol symbol address after reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function rw aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 b7 b6 b5 b4 b3 b2 b1 b0 0 : interrupt disabled 1 : interrupt enabled rw rw (b7-b2) nothing is assigned. when write, set to 0 . when read, their contents are indeterminate. symbol address after reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 address setting register for address match interrupt function setting range address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) rw rw nothing is assigned. when write, set to 0 . when read, its content is indeterminate. (b7-b4) figure 10.17 aier register and rmad0 to rmad1 registers 10.4 address match interrupt
r8c/11 group 11. watchdog timer rev.1.20 jan 27, 2006 page 68 of 204 rej09b0062-0120 11. watchdog timer the watchdog timer is the function of detecting when the program is out of control. therefore, we recom- mend using the watchdog timer to improve reliability of a system. the watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the cpu clock using the prescaler. whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per- formed when the watchdog timer underflows after reaching the terminal count can be selected using the pm12 bit in the pm1 register. the pm12 bit can only be set to 1 (reset). once this bit is set to 1 , it cannot be set to 0 (watchdog timer interrupt) in a program. refer to section 5.3, watchdog timer reset for details. the divide-by-n value for the prescaler can be chosen to be 16 or 128 with the wdc7 bit in the wdc register. the period of watchdog timer can be calculated as given below. the period of watchdog timer is, however, subject to an error due to the prescaler. for example, when cpu clock = 16 mhz and the divide-by-n value for the prescaler= 16, the watchdog timer period is approx. 32.8 ms. note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the wdts register. after that, the watchdog timer is initialized by writing to the wdtr register and the counting continues. in stop mode and wait mode, the watchdog timer and prescaler are stopped. counting is resumed from the held value when the modes or state are released. figure 11.1 shows the block diagram of the watchdog timer. figure 11.2 shows the watchdog timer- related registers. prescaler dividing (16 or 128) x watchdog timer count (32768) cpu clock watchdog timer period = write to wdtr register internal reset signal pm12 = 0 watchdog timer set to 7fff 16 cpu clock 1/128 1/16 wdc7 = 1 wdc7 = 0 prescaler pm12 = 1 watchdog timer interrupt request watchdog timer reset figure 11.1 watchdog timer block diagram
r8c/11 group 11. watchdog timer rev.1.20 jan 27, 2006 page 69 of 204 rej09b0062-0120 watchdog timer start register symbol address after reset wdts 000e 16 indeterminate wo b7 b0 function the watchdog timer starts counting after a write instruction to this register. rw watchdog timer reset register symbol address after reset wdtr 000d 16 indeterminate wo b7 b0 function rw the watchdog is initialized after a write instruction to this register. the watchdog timer value is always initialized to 7fff 16 regardless of whatever value is written. figure 11.2 wdc register, wdtr register, and wdts register w a t c h d o g t i m e r c o n t r o l r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t w d c 0 0 0 1 1 1 1 1 2 0 0 0 x x x x x 2 f u n c t i o n b i t s y m b o lr w b7 b6 b5 b4 b3 b2 b1 b0 h i g h - o r d e r b i t o f w a t c h d o g t i m e r w d c 7 b i t n a m e p r e s c a l e r s e l e c t b i t0 : d i v i d e d b y 1 6 1 : d i v i d e d b y 1 2 8 r e s e r v e d b i tm u s t s e t t o 0 0 r o r w r w r w ( b 4 - b 0 ) ( b 6 ) 0 ( b 5 ) r e s e r v e d b i tm u s t s e t t o 0
r8c/11 group rev.1.20 jan 27, 2006 page 70 of 204 rej09b0062-0120 12. timers the microcomputer has three 8-bit timers and one 16-bit timer. the three 8-bit timers are timer x, timer y, and timer z and each one has an 8-bit prescaler. the 16-bit timer is timer c and has input capture and output compare. all these timers function independently. the count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading. table 12.1 lists functional comparison. item timer x timer y timer z timer c configuration 8-bit timer 8-bit timer 8-bit timer 16-bit with 8-bit with 8-bit with 8-bit free-run prescaler prescaler prescaler timer count down down down up count source f 1 f 1 f 1 f 1 f 2 f 8 f 2 f 8 f 8 f ring f 8 f 32 f 32 input from timer y f ring-fast cntr 1 pin underflow function timer mode provided provided provided not provided pulse output mode provided not provided not provided not provided event counter mode provided provided (1) not provided not provided pulse width measurement mode provided not provided not provided not provided pulse period measurement mode provided not provided not provided not provided programmable waveform generation mode not provided provided provided not provided programmable one-shot generation mode not provided not provided provided not provided programmable wait one-shot generation mode not provided not provided provided not provided input capture mode not provided not provided not provided provided output compare mode not provided not provided not provided provided input pin cntr 0 cntr 1 _____ int 0 tc in output pin cntr 0 cmp0 0 to cmp0 2 __________ cntr 0 cntr 1 tz out cmp1 0 to cmp1 2 related interrupt timer x int timer y int timer z int timer c int _____ int1 int _____ int2 int _____ int0 int _____ int3 int compare 0 int compare 1 int timer stop provided provided provided provided table 12.1 functional comparison notes: 1. select the input from the cntr 1 pin as a count source of timer mode. 12. timers
r8c/11 group rev.1.20 jan 27, 2006 page 71 of 204 rej09b0062-0120 t x c k 1 t o t x c k 0 = 0 0 2 f 1 f 8 f 32 f 2 toggle flip-flop p o l a r i t y s w i t c h i n g q q c k t x o c n t b i t c n t r 0 r 0 e d g = 0 c l r t x m o d 1 t o t x m o d 0 b i t s = 0 1 2 counter reload registe r c o u n t e r r e l o a d r e g i s t e r t x s b i t p r e x r e g i s t e r t x r e g i s t e r w r i t e t o t x r e g i s t e r t i m e r x i n t e r r u p t da t a b u s int1 interrupt i n t 1 / c n t r 0 r 0 e d g = 1 t x m o d 1 t o t x m o d 0 b i t s = 0 1 2 = 0 1 2 = 1 0 2 = 1 1 2 t x m o d 1 t o t x m o d 0 = 0 0 2 o r 0 1 2 = 1 0 2 = 1 1 2 figure 12.1 timer x block diagram t i m e r x m o d e r e g i s t e r symbol address after reset txmr 008b 16 00 16 bit name f u n c t i o n b i t s y m b o l rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : timer mode or pulse period measurement mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 txmod2 t x s t x m o d 1 r 0 e d g t x m o d 0 txocnt i n t 1 / c n t r 0 p o l a r i t y s w i t c h i n g b i t (1 ) o p e r a t i o n m o d e s e l e c t b i t 0 , 1 t i m e r x c o u n t s t a r t f l a g 0 : stops counting 1 : starts counting p 3 0 / c n t r 0 s e l e c t b i t o p e r a t i o n m o d e s e l e c t b i t 2 0 : except in pulse period measurement mode 1 : pulse period measurement mode function varies depending on operation mode t x e d g t x u n d t i m e r x u n d e r f l o w f l a g function varies depending on operation mode. a c t i v e e d g e r e c e p t i o n f l a g f u n c t i o n v a r i e s d e p e n d i n g o n o p e r a t i o n m o d e . r w r w rw r w r w r w r w r w f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e n o t e s : 1 . t h e i r b i t i n t h e i n t 1 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . figure 12.2 txmr register 12.1 timer x the timer x is an 8-bit timer with an 8-bit prescaler. figure 12.1 shows the block diagram of timer x. figures 12.2 and 12.3 show the timer x-related registers. the timer x has five operation modes listed as follows: timer mode: the timer counts an internal count source. pulse output mode: the timer counts an internal count source and outputs the pulses whose polarity is inverted at the timer the timer underflows. event counter mode: the timer counts external pulses. pulse width measurement mode: the timer measures an external pulse's pulse width. pulse period measurement mode:the timer measures an external pulse's period. 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 72 of 204 rej09b0062-0120 figure 12.3 prex register, tx register, and tcss register b i t n a m e function b i t s y m b o l t i m e r x c o u n t s o u r c e s e l e c t b i t (1 ) b 1 b 0 t x c k 1 t x c k 0 t y c k 0 t i m e r y c o u n t s o u r c e s e l e c t b i t (1 ) tzck0 t y c k 1 t z c k 1 must be set to 0 ( b 7 - b 6 ) r e s e r v e d b i t t i m e r z c o u n t s o u r c e s e l e c t b i t (1 ) n o t e s : 1 . a v o i d s w i t c h i n g a c o u n t s o u r c e , w h i l e a c o u n t e r i s i n p r o g r e s s . t i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t s o u r c e . t i m e r c o u n t s o u r c e s e t t i n g r e g i s t e r symbol address after reset tcss 008e 16 00 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f 2 b 3 b 2 0 0 : f 1 0 1 : f 8 1 0 : f r i n g 1 1 : s e l e c t s i n p u t f r o m c n t r 1 p i n b 5 b 4 0 0 : f 1 0 1 : f 8 1 0 : s e l e c t s t i m e r y u n d e r f l o w 1 1 : f 2 r w r w r w r w r w r w r w r w 0 0 symbol address after reset tx 008d 16 ff 16 underflow of prescaler x is counted function timer x register symbol address after reset prex 008c 16 ff 16 b7 b0 rw internal count source is counted function setting range prescaler x register b7 b0 00 16 to ff 16 00 16 to ff 16 internal count source is counted 00 16 to ff 16 externally input pulses are counted 00 16 to ff 16 pulse width of externally input pulses is measured (internal count source is counted) 00 16 to ff 16 pulse period of externally input pulses is measured (internal count source is counted) 00 16 to ff 16 timer mode pulse output mode event counter mode pulse width measurement mode pulse period measurement mode mode rw rw rw rw rw rw rw setting range 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 73 of 204 rej09b0062-0120 12.1.1 timer mode in this mode, the timer counts an internally generated count source (see table 12.2 timer mode specifications ). figure 12.4 shows the txmr register in timer mode. item specification count source f 1 , f 2 , f 8 , f 32 count operation down-count when the timer underflows, the contents in the reload register is reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: set value of prex register, m: set value of tx register count start condition write 1 (count start) to txs bit in txmr register count stop condition write 0 (count stop) to txs bit in txmr register interrupt request generation timing when timer x underflows [timer x interruption] int1/cntr 0 pin function programmable i/o port, or int1 interrupt input cntr 0 pin function programmable i/o port read from timer count value can be read by reading tx register same applies to prex register. write to timer value written to tx register is written to both reload register and counter. same applies to prex register. table 12.2 timer mode specifications figure 12.4 txmr register in timer mode 12.1 timer (timer x) t i m e r x m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t x m r0 0 8 b 1 6 0 0 1 6 bit name f u n c t i o n bit symbol rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : t i m e r m o d e o r p u l s e p e r i o d m e a s u r e m e n t m o d e b1 b0 txmod2 txs txmod1 r0edg txmod0 txocnt o p e r a t i o n m o d e s e l e c t b i t 0 , 1 t i m e r x c o u n t s t a r t f l a g 0 : stops counting 1 : starts counting operation mode select bit 2 00 0 s e t t o " 0 " i n t i m e r m o d e 0 : rising edge 1 : falling edge 0 txedg t x u n d rw rw rw rw rw rw rw rw int1/cntr 0 polarity switching bit (1, 2) s e t t o " 0 " i n t i m e r m o d e s e t t o " 0 " i n t i m e r m o d e 0 : o t h e r t h a n p u l s e p e r i o d m e a s u r e m e n t m o d e n o t e s : 1 . t h e i r b i t i n t h e i n t 1 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 2 . t h i s b i t i s u s e d t o s e l e c t t h e p o l a r i t y o f i n t 1 i n t e r r u p t i n t i m e r m o d e . 00
r8c/11 group rev.1.20 jan 27, 2006 page 74 of 204 rej09b0062-0120 12.1.2 pulse output mode in this mode, the timer counts an internally generated count source, and outputs from the cntr0 pin a pulse whose polarity is inverted each time the timer underflows (see table 12.3 pulse output mode specifications ). figure 12.5 shows txmr register in pulse output mode. item specification count source f 1 , f 2 , f 8 , f 32 count operation down-count when the timer underflows, the contents in the reload register is reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: set value of prex register, m: set value of tx register count start condition write 1 (count start) to txs bit in txmr register count stop condition write 0 (count stop) to txs bit in txmr register interrupt request when timer x underflows [timer x interruption] generation timing int1/cntr 0 pin function pulse output cntr 0 pin function programmable i/o port or inverted output of cntr 0 read from timer count value can be read by reading tx register. same applies to prex register. write to timer value written to tx register is written to both reload register and counter. same applies to prex register. select function _____ int1/cntr 0 polarity switching function polarity level at starting of pulse output can be selected with r0edg bit (1) inverted pulse output function the inverted pulse of cntr0 output polarity can be output from the cntr0 pin (selected by the txocnt bit) notes: 1. the level of the output pulse becomes the level when the pulse output starts when the tx register is written to. table 12.3 pulse output mode specifications figure 12.5 txmr register in pulse output mode timer x mode register s y m b o la d d r e s sa f t e r r e s e t t x m r0 0 8 b 1 6 0 0 1 6 bit name function b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 : p u l s e o u t p u t m o d e b1 b0 t x m o d 2 txs t x m o d 1 r0edg t x m o d 0 txocnt o p e r a t i o n m o d e s e l e c t b i t 0 , 1 0: cntr 0 output starts at "h" 1: cntr 0 output starts at "l" t i m e r x c o u n t s t a r t f l a g 0 : stops counting 1 : starts counting p 3 0 / c n t r 0 s e l e c t b i t 0 : port p3 0 1 : cntr 0 output m u s t s e t t o " 0 " i n p u l s e o u t p u t m o d e 0 0 1 txedg txund 0 0 rw r w r w r w r w r w r w r w r w int1/cntr 0 polarity switching bit (1) m u s t s e t t o " 0 " i n p u l s e o u t p u t m o d e m u s t s e t t o " 0 " i n p u l s e o u t p u t m o d e n o t e s : 1 . t h e i r b i t i n t h e i n t 1 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 75 of 204 rej09b0062-0120 12.1.3 event counter mode in this mode, the timer counts an external signal fed to int1/cntr 0 pin (see table 12.4 event counter mode specifications ). figure 12.6 shows txmr register in event counter mode. item specification count source external signals fed to cntr 0 pin (active edge is selected by program) count operation down count when the timer underflows, the contents in the reload register is reloaded and the count is continued. divide ratio 1/(n+1)(m+1) n: set value of prex register, m: set value of tx register count start condition write 1 (count start) to txs bit in txmr register count stop condition write 0 (count stop) to txs bit in txmr register interrupt request when timer x underflows [timer x interrupt] generation timing int1/cntr 0 pin function _______ count source input (int1 interrupt input) cntr 0 pin function programmable i/o port read from timer count value can be read by reading tx register same applies to prex register. write to timer value written to tx register is written to both reload register and counter. same applies to prex register. select function int1/cntr 0 polarity switching function active edge of count source can be selected with r0edg. t i m e r x m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t x m r0 0 8 b 1 6 0 0 1 6 bit name f u n c t i o n b i t s y m b o l rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 0 : event counter mode b1 b0 t x m o d 2 t x s t x m o d 1 r 0 e d g t x m o d 0 t x o c n t o p e r a t i o n m o d e s e l e c t b i t 0 , 1 t i m e r x c o u n t s t a r t f l a g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g 0 0 s e t t o " 0 " i n e v e n t c o u n t e r m o d e 0 : r i s i n g e d g e 1 : f a l l i n g e d g e 0 t x e d g t x u n d r w r w rw r w r w r w r w r w i n t 1 / c n t r 0 p o l a r i t y s w i t c h i n g b i t (1 ) s e t t o " 0 " i n e v e n t c o u n t e r m o d e s e t t o " 0 " i n e v e n t c o u n t e r m o d e n o t e s : 1 . t h e i r b i t i n t h e i n t 1 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 00 1 s e t t o " 0 " i n e v e n t c o u n t e r m o d e figure 12.6 txmr register in event counter mode table 12.4 event counter mode specifications 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 76 of 204 rej09b0062-0120 12.1.4 pulse width measurement mode in this mode, the timer measures the pulse width of an external signal fed to int1/cntr0 pin (see table 12.5 pulse width measurement mode specifications ). figure 12.7 shows the txmr register in pulse width measurement mode. figure 12.8 shows an operation example in pulse width measure- ment mode. item specification count source f 1 , f 2 , f 8 , f 32 count operation down-count continuously counts the selected signal only when the measurement pulse is "h" level, or conversely only "l" level. when the timer underflows, the contents in the reload register is reloaded and the count is continued. count start condition write 1 (count start) to txs bit in txmr register count stop condition write 0 (count stop) to txs bit in txmr register interrupt request when timer x underflows [timer x interruption] generation timing rising or falling of cntr0 input (end of measurement period) [int1 interrupt] int1/cntr 0 pin function measurement pulse input cntr 0 pin function programmable i/o port read from timer count value can be read by reading tx register same applies to prex register. write to timer value written to tx register is written to both reload register and counter. same applies to prex register. select function _____ int1/cntr 0 polarity switching function h or l level duration can be selected with r0edg bit as the input pulse measurement table 12.5 pulse width measurement mode specifications figure 12.7 txmr register in pulse width measurement mode 12.1 timer (timer x) t i m e r x m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t x m r0 0 8 b 1 6 0 0 1 6 b i t n a m e f u n c t i o n b i t s y m b o l r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b 1 b 0 t x m o d 1 r 0 e d g t x m o d 0 o p e r a t i o n m o d e s e l e c t b i t 0 , 1 0 1 0 r w r w r w i n t 1 / c n t r 0 p o l a r i t y s w i t c h i n g b i t (1 ) n o t e s : 1 . i t h e i r b i t i n t h e i n t 1 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 00 1 1 1 : pulse width measurement mode txmod2 t x s t x o c n t t i m e r x c o u n t s t a r t f l a g 0 : stops counting 1 : starts counting s e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e t x e d g t x u n d r w r w rw rw rw s e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e s e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e s e t t o " 0 " i n p u l s e w i d t h m e a s u r e m e n t m o d e [cntr0] 0 : measures h level width 1 : measures l level width [int1] 0 : rising edge 1 : falling edge
r8c/11 group rev.1.20 jan 27, 2006 page 77 of 204 rej09b0062-0120 ffff 16 n 0000 16 counter contents (hex) n = high-level: the contents of tx register, low-level: the contents of prex register count stop set to "1" by program count start underflow txs bit in txmr register measurement pulse (cntr0 pin input) ir bit in int1ic register conditions: "h" level width of measurement pulse is measured. (r0edg=1) 1 0 ir bit in txic register cleared to 0 when interrupt request is accepted, or cleared by program h l 1 0 1 0 count stop count restart time cleared to 0 when interrupt request is accepted, or cleared by program figure 12.8 operation example in pulse width measurement mode 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 78 of 204 rej09b0062-0120 12.1.5 pulse period measurement mode in this mode, the timer measures the pulse period of an external signal fed to int1/cntr0 pin (see table 12.6 pulse period measurement mode specifications ). figure 12.9 shows the txmr register in pulse period measurement mode. figure 12.10 shows an operation example in pulse period mea- surement mode. item specification count source f 1 , f 2 , f 8 , f 32 count operation down-count after an active edge of measurement pulse is input, contents in the read-out buffer is retained in the first underflow of prescaler x. then the timer x reloads contents in the reload register in the second underflow of prescaler x and continues counting. count start condition write 1 (count start) to txs bit in txmr register count stop condition write 0 (count stop) to txs bit in txmr register interrupt request when timer x underflows or reloads [timer x interrupt] generation timing _____ rising or falling of cntr0 input (end of measurement period) [int1 interrupt] int1/cntr 0 pin function measurement pulse input (1) (int1 interrupt input) cntr 0 pin function programmable i/o port read from timer contents in the read-out buffer can be read by reading tx register. the value retained in the read-out buffer is released by reading tx register. write to timer value written to tx register is written to both reload register and counter. same applies to prex register. select function _____ int1/cntr0 polarity switching function measurement period of input pulse can be selected with r0edg bit. notes: 1. the period of input pulse must be longer than twice the period of prescaler x. longer pulse for h width and l width than the prescaler x period must be input. if shorter pulse than the period is input to the cntr0 pin, the input may be disabled. table 12.6 pulse period measurement mode specifications t i m e r x m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t x m r0 0 8 b 1 6 0 0 1 6 b i t n a m e function bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : timer mode or pulse period measurement mode b1 b0 t x m o d 1 r0edg t x m o d 0 int1/cntr0 polarity switching bit (1) operation mode select bit 0, 1 1 0 0 0 n o t e s : 1 . t h e i r b i t i n t h e i n t 1 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 0 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 2 . t h i s b i t i s s e t t o 0 b y w r i t i n g 0 i n a p r o g r a m . ( i t r e m a i n s u n c h a n g e d e v e n i f w r i t i n g 1 ) rw r w r w r w t x m o d 2 t x s t x o c n t timer x count start flag 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g o p e r a t i o n m o d e s e l e c t b i t 2 1 : p u l s e p e r i o d m e a s u r e m e n t m o d e s e t t o 0 i n p u l s e p e r i o d m e a s u r e m e n t m o d e t x e d g (2 ) t x u n d (2 ) t i m e r x u n d e r f l o w f l a g 0 : n o u n d e r f l o w 1 : u n d e r f l o w f o u n d 0 : no active edge 1 : active edge found a c t i v e e d g e j u d g m e n t f l a g r w r w r w r w r w [cntr 0 ] 0: measures a measurement pulse from one rising edge to the next rising edge 1: measures a measurement pulse from one falling edge to the next falling edge [int1] 0: rising edge 1: falling edge figure 12.9 txmr register in pulse period measurement mode 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 79 of 204 rej09b0062-0120 0 f 1 6 0 e 1 6 0e 1 6 0d 16 0 c 1 6 0 b 1 6 0 a 1 6 0 9 1 6 0f 16 0e 1 6 0d 16 01 1 6 0 0 1 6 0 f 1 6 0 e 1 6 0 f 1 6 0e 1 6 0 a 1 6 08 1 6 t i m e r x r e l o a d s 0 d 1 6 0 1 1 6 0 f 1 6 0 e 1 6 timer x read t x e d g b i t i n t x m r r e g i s t e r (2) cleared to "0" by program txund bit in txmr register notes: 1. the contents of the read-out buffer can be read when the tx register is read in pulse period measurement mode. 2. after an active edge of measurement pulse is input, the txedg bit in the txmr register is set to "1" (active edge found) when the prescaler x underflows for the second time. 3. the tx register should be read before the next active edge is input after the txedg bit is set to "1" (active edge found). the contents in the read-out buffer is retained until the tx register is read. if the tx register is not read before the next active edge is input, the measured result of the previous period is retained. 4. when set to "0" by program, use a mov instruction to write "0" to the txedg in the txmr register. at the same time, write "1" to the txund bit. 5. when set to "0" by program, use a mov instruction to write "0" to the txund in the txmr register. at the same time, write "1" to the txedg bit. 6. the txund and txedg bits are both set to "1" if the timer underflows and reloads on an active edge simultaneously. in this case, the validity of the txund bit should be determined by the contents of the read-out buffer. 7. if the cntr 0 active edge is input, when the prescaler x underflow signal is "h" level, its count value is the one of the read buffer. if "l" level, the following count value is the one of the read buffer. c o n d i t i o n s : a p e r i o d f r o m o n e r i s i n g e d g e t o t h e n e x t r i s i n g e d g e o f m e a s u r e m e n t p u l s e i s m e a s u r e d ( r 0 e d g = 0 ) w i t h t x r e g i s t e r i n i t i a l v a l u e = 0 f 1 6 . s e t t o " 1 " b y p r o g r a m s t a r t s c o u n t i n g t x s b i t i n t x m r r e g i s t e r 1 0 1 0 c n t r 0 p i n i n p u t t i m e r x c o n t e n t s c o n t e n t s o f r e a d - o u t b u f f e r 1 timer x reloads t i m e r x r e l o a d s t i m e r x r e a d (2) (4) (6) c l e a r e d t o " 0 " b y p r o g r a m 1 0 1 0 1 0 1 0 cleared to 0 when interrupt request is accepted, or cleared by program cleared to 0 when interrupt request is accepted, or cleared by program i r b i t i n i n t 1 i c r e g i s t e r ir bit in txic register 09 1 6 0 0 1 6 r e t a i n e d retained 0 8 1 6 0f 16 u n d e r f l o w s i g n a l o f p r e s c a l e r x (3) (3) ( 7 )( 7 ) (5) figure 12.10 operation example in pulse period measurement mode 12.1 timer (timer x)
r8c/11 group rev.1.20 jan 27, 2006 page 80 of 204 rej09b0062-0120 12.2 timer y timer y is an 8-bit timer with an 8-bit prescaler and has two reload registers-timer y primary and timer y secondary. figure 12.11 shows a block diagram of timer y. figures 12.12 to 12.14 show the tyzmr, prey, tysc, typr, tyzoc, pum, and ycss registers. the timer y has two operation modes as follows: timer mode: the timer counts an internal count source (clock source). programmable waveform generation mode: the timer outputs pulses of a given width successively. figure 12.11 timer y block diagram figure 12.12 tyzmr register toggle flip-flop timer y interrupt int2 i nterrupt f 1 f 8 q c k f r i n g tysc register t y o c n t = 1 tyopl=1 q tyopl=0 p 3 _ 2 b i t i n p 3 r e g i s t e r t y o c n t = 0 tymod0=1 t y s = 1 prey register i n t 2 / c n t r 1 t y c k 1 t o t y c k 0 = 0 0 2 = 0 1 2 = 1 0 2 = 1 1 2 counter reload register c o u n t e r r e l o a d r e g i s t e r da t a b u s reload register p o l a r i t y s w i t c h i n g clr write to tyzmr register t y m o d 0 b i t = 1 t y p r r e g i s t e r t i m e r y , z m o d e r e g i s t e r symbol address after reset tyzmr 0080 16 00 16 b i t n a m e f u n c t i o n bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : timer mode 0 1 : programmable waveform generation mode 1 0 : programmable one-shot generation mode 1 1 : programmable wait one-shot generation mode t z m o d 1 tys t y w c t y m o d 0 t z m o d 0 t i m e r y o p e r a t i o n m o d e b i t t i m e r y w r i t e c o n t r o l b i t f u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e 0 : t i m e r m o d e 1 : p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e t z w c t z s 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g 0 : stops counting 1 : starts counting t i m e r z c o u n t s t a r t f l a g timer z operation mode bit b5 b4 t i m e r y c o u n t s t a r t f l a g t i m e r z w r i t e c o n t r o l b i t f u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e r w r w r w r w r w r w r w r w r w r 1 e d g 0 : r i s i n g e d g e 1 : f a l l i n g e d g e i n t 2 / c n t r 1 p o l a r i t y s w i t c h i n g b i t (1 ) n o t e s : 1 . t h e i r b i t i n t h e i n t 2 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 1 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 81 of 204 rej09b0062-0120 t i m e r y , z o u t p u t c o n t r o l r e g i s t e r ( 3 ) s y m b o la d d r e s sa f t e r r e s e t t y z o c0 0 8 a 1 6 0 0 1 6 bit name function b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t z o c n t t y o c n t t z o s n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o " 0 " . w h e n r e a d , i t s c o n t e n t i s " 0 " . t i m e r z o n e - s h o t s t a r t b i t ( 1 ) t i m e r y p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n o u t p u t s w i t c h i n g b i t ( 2 ) 0 : o u t p u t s p r o g r a m m a b l e w a v e f o r m 1 : o u t p u t s t h e v a l u e o f p 3 2 p o r t r e g i s t e r 0 : o u t p u t s p r o g r a m m a b l e w a v e f o r m 1 : o u t p u t s t h e v a l u e o f p 3 1 p o r t r e g i s t e r 0 : s t o p s o n e - s h o t 1 : s t a r t s o n e - s h o t timer z programmable waveform generation output switching bit (2) n o t e s : 1 . t h i s b i t i s s e t t o " 0 " w h e n t h e o u t p u t o f o n e - s h o t w a v e f o r m i s c o m p l e t e d . t h e t z o s b i t s h o u l d b e s e t t o " 0 " i f t h e o n e - s h o t w a v e f o r m o u t p u t i s t e r m i n a t e d b y s e t t i n g t h e t z s b i t i n t h e t y z m r t o " 0 " d u r i n g t h e w a v e f o r m o u t p u t . 2 . t h i s b i t i s e n a b l e d o n l y w h e n o p e r a t i n g i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e . 3 . i f e x e c u t i n g a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e t z o s b i t i s 1 ( d u r i n g t h e c o u n t ) , t h e t z o s i s a u t o m a t i c a l l y s e t t o 0 w h e n t h e c o u n t c o m p l e t e s w h i l e t h e i n s t r u c t i o n i s e x e c u t e d . i f t h i s c a u s e s s o m e p r o b l e m s , e x e c u t e a n i n s t r u c t i o n w h i c h c h a n g e s t h i s r e g i s t e r w h e n t h e t z o s b i t i s 0 ( o n e s h o t s t o p ) . r w r w r w r w ( b 7 - b 3 ) figure 12.13 prey register, tysc register, typr register, and tyzoc register timer y primary register timer y secondary register symbol address after reset tysc 0082 16 ff 16 notes: 1. the values of typr register and tysc register are reloaded to the counter alternately for counting. 2. the count value can be read out by reading the typr register even when the secondary period is being counted. symbol address after reset prey 0081 16 ff 16 b0 rw internal count source or cntr1 input is counted function setting range prescaler y register 00 16 to ff 16 internal count source is counted 00 16 to ff 16 timer mode programmable waveform generation mode mode rw rw symbol address after reset typr 0083 16 ff 16 b7 rw disabled function setting range underflow of prescaler y is counted (1) 00 16 to ff 16 timer mode programmable waveform generation mode mode wo (2) rw underflow of prescaler y is counted function setting range underflow of prescaler y is counted (1) 00 16 to ff 16 timer mode programmable waveform generation mode mode 00 16 to ff 16 rw rw notes: 1. the values of typr register and tysc register are reloaded to the counter alternately for counting. b0 b7 b0 b7 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 82 of 204 rej09b0062-0120 bit name function bit symbol t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t p u m0 0 8 4 1 6 0 0 1 6 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 n o t e s : 1 . t h e i n o s e g b i t i s v a l i d o n l y w h e n t h e i n t 0 p l b i t i n t h e i n t e n r e g i s t e r i s " 0 " ( o n e - e d g e ) . 2 . t h e i n o s g t b i t m u s t b e s e t t o " 1 " a f t e r t h e i n t 0 e n b i t i n t h e i n t e n r e g i s t e r a n d t h e i n o s e g b i t i n t h e p u m r e g i s t e r a r e s e t . 0 0 0 0 t y o p l tzopl inoseg i n o s t g int0 pin one-shot trigger polarity select bit (1) timer z output level latch t i m e r y o u t p u t l e v e l l a t c h i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t (2 ) function varies depending on the operation mode function varies depending on the operation mode 0 : edge trigger at falling edge 1 : edge trigger at rising edge (timer z) (timer z) 0 : int0 pin one-shot trigger invalid 1 : int0 pin one-shot trigger valid ( b 3 - b 0 ) r e s e r v e d b i t must set to 0 rw rw r w rw r w rw figure 12.14 pum register and tcss register b i t n a m e function b i t s y m b o l timer x count source select bit (1) b 1 b 0 txck1 txck0 t y c k 0 t i m e r y c o u n t s o u r c e s e l e c t b i t (1 ) t z c k 0 tyck1 t z c k 1 s e t t o 0 ( b 7 - b 6 ) reserved bit timer z count source select bit (1) n o t e s : 1 . a v o i d s w i t c h i n g a c o u n t s o u r c e , w h i l e a c o u n t e r i s i n p r o g r e s s . t i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t s o u r c e . t i m e r c o u n t s o u r c e s e t t i n g r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t c s s0 0 8 e 1 6 0 0 1 6 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f 2 b3 b2 0 0 : f 1 0 1 : f 8 1 0 : f ring 1 1 : selects input from cntr 1 pin b5 b4 0 0 : f 1 0 1 : f 8 1 0 : selects timer y underflow 1 1 : f 2 r w r w r w r w r w r w r w r w 0 0 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 83 of 204 rej09b0062-0120 12.2.1 timer mode in this mode, the timer counts an internally generated count source (see table 12.7 timer mode specifications ). an external signal input to the cntr1 pin can be counted. the tysc register is unused in timer mode. figure 12.15 shows the tyzmr and pum registers in timer mode. item specification count source f 1 , f 8 , f ring , external signal fed to cntr1 pin count operation down-count when the timer underflows, it reloads the reload register contents before continuing counting (when the timer y underflows, the contents of the timer y primary reload register is reloaded.) divide ratio 1/(n+1)(m+1) n: set value in prey register, m: set value in typr register count start condition write 1 (count start) to tys bit in tyzmr register count stop condition write 0 (count stop) to tys bit in tyzmr register interrupt request when timer y underflows [timer y interrupt] generation timing int2/cntr 1 pin function _______ _______ programmable i/o port, count source input or int2 interrupt input when the tyck1 to tyck0 bits in the tcss register are set to 00b , 01b or 10b _______ (timer y count source is f 1 , f 8 or f ring ), programmable i/o port or int2 interrupt input when the tyck1 to tyck0 bits are set to 11b (timer y count source is cntr 1 _______ input), count source input (int2 interrupt input) read from timer count value can be read out by reading typr register. same applies to prey register. write to timer (1) value written to typr register is written to both reload register and counter or written to only reload register. selected by program. same applies to prey register. select function event counter function when setting tyck1 to tyck0 bits to 11 2 , an external signal fed to cntr1 pin is counted. _______ int2/cntr1 switching bit active edge of count source is selected by r1edg bit. notes: 1. the ir bit in the tyic register is set to "1" (interrupt requested) if you write to the typr or prey register while both of the following conditions are met. conditions: tywc bit in tyzmr register is "0" (write to reload register and counter simultaneously) tys bit is "1" (count start) to write to the typr or prey register in the above state, disable interrupts before writing. table 12.7 timer mode specifications 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 84 of 204 rej09b0062-0120 figure 12.15 tyzmr register and pum register in timer mode t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 bit name f u n c t i o n bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t z m o d 1 tys tywc tymod0 tzmod0 timer y operation mode bit n o t e s : 1 . t h e i r b i t i n t h e i n t 2 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 1 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . 2 . w h e n t y s b i t = 1 ( s t a r t s c o u n t i n g ) , t h e v a l u e s e t i n t h e t y w c b i t i s v a l i d . i f t y w c b i t = 0 , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r . i f t y w c b i t = 1 , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y . w h e n t y s b i t = 0 ( s t o p s c o u n t i n g ) , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r r e g a r d l e s s o f h o w t h e t y w c b i t i s s e t . timer y write control bit (2) 0 : t i m e r m o d e t z w c t z s 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g timer z-related bit timer y count start flag 0 r w r w r w r w rw r w r 1 e d g 0 : r i s i n g e d g e 1 : f a l l i n g e d g e int2/cntr1 polarity switching bit (1) r w rw rw 0 : w r i t e t o r e l o a d r e g i s t e r a n d c o u n t e r s i m u l t a n e o u s l y 1 : w r i t e t o r e l o a d r e g i s t e r bit name function bit symbol tyopl tzopl inoseg inostg timer z-related bits timer y, z waveform output control register symbol address after reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer y output level latch invalid in timer mode 0 0 0 0 (b3-b0) reserved bit must set to 0 rw rw rw rw rw rw 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 85 of 204 rej09b0062-0120 in this mode, an signal output from the ty out pin is inverted each time the counter underflows, while the values in the typr register and tysc register are counted alternately (see table 12.8 program- mable waveform generation mode specifications ). a counting starts by counting the set value in the typr register. figure 12.16 shows the tyzmr register in programmable waveform generation mode. figure 12.17 shows the operation example. item specification count source f 1 , f 8 , f ring count operation down count when the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting. output waveform width primary period : (n+1)(m+1)/f i and period secondary period : (n+1)(p+1)/f i period : (n+1){(m+1)+(p+1)}/f i n: set value in prey register, m: set value in typr register, p: set value in tysc register f i : count source frequency count start condition write 1 (count start) to tys bit in tyzmr register count stop condition write 0 (count stop) to tys bit in tyzmr register interrupt request generation timing in half of count source, after timer y underflows during secondary period (at the same time as the cntr 1 output change) [timer y interrupt]. _______ int2/cntr 1 pin functions pulse output use timer mode when using this pin as a programmable i/o port. read from timer count value can be read out by reading typr register. same applies to prey register (1) . write to timer value written to typr register is written to only reload register. same applies to tysc register and prey register (2) . select function output level latch select function the output level during primary and secondary periods is selected by the tyopl bit. programmable waveform generation output switching function when the tyocnt bit in the tyzoc register is set to 0 , the output from ty out is inverted synchronously when timer y underflows during the secondary period. and when set to 1 , a value in the p3_2 bit is output from ty out synchronously when timer y underflows during the secondary period (3) . notes: 1. even when counting the secondary period, read out the typr register. 2. the set value in the typr register and tysc register are made effective by writing a value to the typr register. the written values are reflected to the waveform output from the next primary period after writing to the typr register. 3. the tyocntbit is enabled in the following timings when count starts when timer y interrupt request is generated therefore, pulse is output from the next primary period depending on the setting value of the tyocnt bit. table 12.8 programmable waveform generation mode specifications 12.2.2 programmable waveform generation mode 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 86 of 204 rej09b0062-0120 figure 12.16 tyzmr register and pum register in programmable waveform generation mode t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 b i t n a m e f u n c t i o n bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 tzmod1 t y s t y w c tymod0 tzmod0 timer y operation mode bit notes: 1. the ir bit in the int2ic register may be set to 1 (interrupt requested) when the r1edg bit is rewritten. refer to the paragraph 19.2.5 changing interrupt factor in the usage notes reference book. 1 : p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e tzwc tzs 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g timer z-related bit timer y count start flag 1 timer y write control bit r w r w r w r w r w rw r 1 e d g disabled in programmable waveform generation mode i n t 2 / c n t r 1 p o l a r i t y s w i t c h i n g b i t (1 , 3 ) r w r w r w 2 . w h e n t y s b i t = 1 ( s t a r t s c o u n t i n g ) , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y . w h e n t y s b i t = 0 ( s t o p s c o u n t i n g ) , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r . 3 . t h e i n t 2 i n t e r r u p t r e q u e s t i s n o t g e n e r a t e d w h e n t h e t y m o d 0 b i t i s s e t t o 1 ( p r o g r a m m a b l e w a v e f o r m g e n e r a t i o m o d e ) . must set to "1" in programmable waveform generation mode. (2) 1 bit name function bit symbol tyopl tzopl inoseg inostg timer z-related bits timer y, z waveform output control register symbol address after reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 timer y output level latch 0 : outputs "h" for primary period outputs "l" for secondary period outputs "l" when the timer is stopped 1 : outputs "l" for primary period outputs "h" for secondary period outputs "h" when the timer is stopped (b3-b0) reserved bit must set to 0 rw rw rw rw rw rw 0 0 0 0 12.2 timer (timer y)
r8c/11 group rev.1.20 jan 27, 2006 page 87 of 204 rej09b0062-0120 figure 12.17 timer y operation example in programmable waveform generation mode 12.2 timer (timer y) cntr1 pin output "h" "l" ir bit in tyic register "1" "0" tys bit in tyzmr register "1" "0" set to "1" by program count starts 01 16 00 16 02 16 set to "0" when interrupt request is accepted, or set by program waveform output started waveform output inverted waveform output inverted "1" "0" tyopl bit in pum register contents of timer y count source primary period secondary period primary period prescaler y underflow signal 01 16 00 16 01 16 00 16 02 16 timer y primary reloads timer y secondary reloads conditions: prey=01 16 , typr=01 16, tysc=02 16 tyzoc register tyocnt bit = 0 set to "0" by program
r8c/11 group rev.1.20 jan 27, 2006 page 88 of 204 rej09b0062-0120 t z s c r e g i s t e r f 1 f 8 t i m e r y u n d e r f l o w f 2 t o g g l e f l i p - f l o p p3_1 bit in p3 register tz ou t q q da t a b u s r e l o a d r e g i s t e r r e l o a d r e g i s t e r reload registe r c o u n t e r c o u n t e r p r e z r e g i s t e r i n p u t p o l a r i t y s e l e c t e d t o b e o n e e d g e o r b o t h e d g e s d i g i t a l f i l t e r polarity select i n t 0 t z s t z o s inoseg tzocnt=0 int0p l t z m o d 1 t o t z m o d 0 = 0 1 2 , 1 0 2 , 1 1 2 int0en t z o c n t = 1 tzopl=0 t z o p l = 1 tzmod1 to tzmod0=10 2 , 11 2 t z c k 1 t o t z c k 0 = 0 0 2 = 0 1 2 = 1 0 2 = 1 1 2 timer z interrup t i n t 0 i n t e r r u p t c k clr w r i t e t o t y z m r r e g i s t e r tzmod1 to tzmod0 bits=01 2 , 10 2 , 11 2 t z p r r e g i s t e r figure 12.19 tyzmr register 12.3 timer z timer z is an 8-bit timer with an 8-bit prescaler and has two reload registers-timer z primary and timer z secondary. figure 12.18 shows a block diagram of timer z. figures 12.19 to 12.21 show the tyzmr, prez, tzsc, tzpr, tyzoc, pum, and tcss registers. timer z has the following four operation modes. ?timer mode: the timer counts an internal count source or timer y underflow. ?programmable waveform generation mode: the timer outputs pulses of a given width successively. ?programmable one-shot generation mode: the timer outputs one-shot pulse. t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 bit name function b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : t i m e r m o d e 0 1 : p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e 1 0 : p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e 1 1 : p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e tzmod1 tys t y w c t y m o d 0 tzmod0 timer y operation mode bit timer y write control bit f u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e 0 : t i m e r m o d e 1 : p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e t z w c t z s 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g timer z count start flag timer z operation mode bit b 5 b 4 timer y count start flag timer z write control bit f u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e r w r w r w r w r w r w r w r w r w r 1 e d g 0 : r i s i n g e d g e 1 : f a l l i n g e d g e int2/cntr 1 polarity switching bit (1) n o t e s : 1 . t h e i r b i t i n t h e i n t 2 i c r e g i s t e r m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e r 1 e d g b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . figure 12.18 timer z block diagram programmable wait one-shot generation mode: the timer outputs delayed one-shot pulse. 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 89 of 204 rej09b0062-0120 figure 12.20 prez register, tzsc register, tzpr register, and tyzoc register n o t e s : 1 . e a c h v a l u e i n t h e t z p r r e g i s t e r a n d t z s c r e g i s t e r i s r e l o a d e d t o t h e c o u n t e r a l t e r n a t e l y f o r c o u n t i n g . 2 . t h e c o u n t v a l u e c a n b e r e a d o u t b y r e a d i n g t h e t z s c r e g i s t e r e v e n w h e n t h e s e c o n d a r y p e r i o d i s b e i n g c o u n t e d . n o t e s : 1 . e a c h v a l u e i n t h e t z p r r e g i s t e r a n d t z s c r e g i s t e r i s r e l o a d e d t o t h e c o u n t e r a l t e r n a t e l y f o r c o u n t i n g . s y m b o la d d r e s sa f t e r r e s e t p r e z0 0 8 5 1 6 f f 1 6 b 7 b 0 r w i n t e r n a l c o u n t s o u r c e o r t i m e r y u n d e r f l o w i s c o u n t e d f u n c t i o ns e t t i n g r a n g e p r e s c a l e r z r e g i s t e r 0 0 1 6 t o f f 1 6 i n t e r n a l c o u n t s o u r c e o r t i m e r y u n d e r f l o w i s c o u n t e d 0 0 1 6 t o f f 1 6 i n t e r n a l c o u n t s o u r c e o r t i m e r y u n d e r f l o w i s c o u n t e d0 0 1 6 t o f f 1 6 t i m e r m o d e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e m o d e r w r w r w i n t e r n a l c o u n t s o u r c e o r t i m e r y u n d e r f l o w i s c o u n t e d 0 0 1 6 t o f f 1 6 p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e r w s y m b o la d d r e s sa f t e r r e s e t t z s c0 0 8 6 1 6 f f 1 6 b 7 b 0 r w i n v a l i d f u n c t i o ns e t t i n g r a n g e t i m e r z s e c o n d a r y r e g i s t e r u n d e r f l o w o f p r e s c a l e r z i s c o u n t e d ( 1 ) 0 0 1 6 t o f f 1 6 i n v a l i d t i m e r m o d e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e m o d e w o ( 2 ) u n d e r f l o w o f p r e s c a l e r z i s c o u n t e d ( o n e - s h o t w i d t h i s c o u n t e d ) 0 0 1 6 t o f f 1 6 p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e w o s y m b o la d d r e s sa f t e r r e s e t t z p r0 0 8 7 1 6 f f 1 6 b 7 b 0 r w u n d e r f l o w o f p r e s c a l e r z i s c o u n t e d f u n c t i o ns e t t i n g r a n g e t i m e r z p r i m a r y r e g i s t e r 0 0 1 6 t o f f 1 6 u n d e r f l o w o f p r e s c a l e r z i s c o u n t e d ( 1 ) 0 0 1 6 t o f f 1 6 u n d e r f l o w o f p r e s c a l e r z i s c o u n t e d ( o n e - s h o t w i d t h i s c o u n t e d ) 0 0 1 6 t o f f 1 6 t i m e r m o d e p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e m o d e r w r w r w u n d e r f l o w o f p r e s c a l e r z i s c o u n t e d ( w a i t p e r i o d i s c o u n t e d ) 0 0 1 6 t o f f 1 6 p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e r w t i m e r y , z o u t p u t c o n t r o l r e g i s t e r ( 3 ) s y m b o la d d r e s sa f t e r r e s e t t y z o c0 0 8 a 1 6 0 0 1 6 bit name function b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t z o c n t t y o c n t t z o s n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o " 0 " . w h e n r e a d , i t s c o n t e n t i s " 0 " . t i m e r z o n e - s h o t s t a r t b i t ( 1 ) t i m e r y p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n o u t p u t s w i t c h i n g b i t ( 2 ) 0 : o u t p u t s p r o g r a m m a b l e w a v e f o r m 1 : o u t p u t s t h e v a l u e o f p 3 2 p o r t r e g i s t e r 0 : outputs programmable waveform 1 : outputs the value of p3 1 port register 0 : stops one-shot 1 : starts one-shot t i m e r z p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n o u t p u t s w i t c h i n g b i t ( 2 ) notes: 1. this bit is set to "0" when the output of one-shot waveform is completed. the tzos bit should be set to "0" if the one-shot waveform output is terminated by setting the tzs bit in the tyzmr to "0" during the waveform output. 2. this bit is enabled only when operating in programmable waveform generation mode. 3. if executing an instruction which changes this register when the tzos bit is 1 (during the count), the tzos is automatically set to 0 when the count completes while the instruction is executed. if this causes some problems, execute an instruction which changes this register when the tzos bit is 0 (one shot stop). rw rw rw rw ( b 7 - b 3 ) 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 90 of 204 rej09b0062-0120 figure 12.21 pum register and tcss register bit name f u n c t i o n b i t s y m b o l t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t p u m0 0 8 4 1 6 0 0 1 6 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 notes: 1. the inoseg bit is valid only when the int0pl bit in the inten register is "0" (one-edge). 2. the inosgt bit must be set to "1" after the int0en bit in the inten register and the inoseg bit in the pum register are set. 0 0 0 0 tyop l tzopl i n o s e g i n o s t g i n t 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t (1 ) timer z output level latch t i m e r y o u t p u t l e v e l l a t c h i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t (2 ) f u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e f u n c t i o n v a r i e s d e p e n d i n g o n t h e o p e r a t i o n m o d e 0 : e d g e t r i g g e r a t f a l l i n g e d g e 1 : e d g e t r i g g e r a t r i s i n g e d g e (timer z) (timer z) 0 : i n t 0 p i n o n e - s h o t t r i g g e r i n v a l i d 1 : i n t 0 p i n o n e - s h o t t r i g g e r v a l i d ( b 3 - b 0 ) r e s e r v e d b i t s e t t o 0 r w r w r w r w r w rw bit name f u n c t i o n bit symbol timer x count source select bit (1) b1 b0 txck1 txck0 t y c k 0 timer y count source select bit (1) tzck0 t y c k 1 tzck1 set to 0 ( b 7 - b 6 ) r e s e r v e d b i t timer z count source select bit (1) n o t e s : 1 . a v o i d s w i t c h i n g a c o u n t s o u r c e , w h i l e a c o u n t e r i s i n p r o g r e s s . t i m e r c o u n t e r m u s t b e s t o p p e d b e f o r e s w i t c h i n g a c o u n t s o u r c e . timer count source setting register symbol address after reset tcss 008e 16 00 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f 2 b3 b2 0 0 : f 1 0 1 : f 8 1 0 : f r i n g 1 1 : s e l e c t s i n p u t f r o m c n t r 1 p i n b5 b4 0 0 : f 1 0 1 : f 8 1 0 : s e l e c t s t i m e r y u n d e r f l o w 1 1 : f 2 rw rw rw rw r w rw rw r w 0 0 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 91 of 204 rej09b0062-0120 12.3.1 timer mode in this mode, the timer counts an internally generated count source or timer y underflow (see table 12.9 timer mode specifications ). the tzsc register is unused in timer mode. figure 12.22 shows the tyzmr register and pum register in timer mode. item specification count source f 1 , f 2 , f 8 , timer y underflow count operation down-count when the timer underflows, it reloads the reload register contents before continuing counting (when the timer z underflows, the contents of the timer z primary reload register is reloaded.) divide ratio 1/(n+1)(m+1) n: set value in prez register, m: set value in tzpr register count start condition write 1 (count start) to tzs bit in tyzmr register count stop condition write 0 (count stop) to tzs bit in tyzmr register interrupt request when timer z underflows [timer z interrupt] generation timing tz out pin function programmable i/o port int0 pin function _______ programmable i/o port, or int0 interrupt input read from timer count value can be read out by reading tzpr register. same applies to prez register. write to timer (1) value written to tzpr register is written to both reload register and counter or written to reload register only. selected by program. same applies to prez register. notes: 1. the ir bit in the tzic register is set to "1" (interrupt requested) if you write to the tzpr or prez register while both of the following conditions are met. tzwc bit in tyzmr register is set to "0" (write to reload register and counter simultaneously) tzs bit in tyzmr register is set to "1" (count start) to write to the tzpr or prez register in the above state, disable interrupts before the writing. table 12.9 timer mode specifications 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 92 of 204 rej09b0062-0120 figure 12.22 tyzmr register and pum register in timer mode t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 bit name f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : timer mode t z m o d 1 tys t y w c tymod0 t z m o d 0 t i m e r y - r e l a t e d b i t tzwc tzs 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b5 b4 t i m e r z w r i t e c o n t r o l b i t (1 ) 0 : write to reload register and counter 1 : write to reload register only 0 0 r w r w rw r w r w rw r w r w r 1 e d g r w n o t e s : 1 . w h e n t z s b i t = 1 ( s t a r t s c o u n t i n g ) , t h e v a l u e s e t i n t h e t z w c b i t i s v a l i d . i f t z w c b i t = 0 , t h e t i m e r z c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r . i f t z w c b i t = 1 , t h e t i m e r z c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y . w h e n t z s b i t = 0 ( s t o p s c o u n t i n g ) , t h e t i m e r z c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r r e g a r d l e s s o f h o w t h e t z w c b i t i s s e t . bit name function bit symbol timer y, z waveform output control register symbol address after reset pum 0084 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 tyopl tzopl inoseg inostg timer z output level latch must set to 0 in timer mode int0 pin one-shot trigger control bit int0 pin one-shot trigger polarity select bit (b3-b0) reserved bit must set to 0 rw rw rw rw rw rw timer y-related bit must set to 0 in timer mode must set to 0 in timer mode 0 0 0 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 93 of 204 rej09b0062-0120 12.3.2 programmable waveform generation mode in this mode, an signal output from the tz out pin is inverted each time the counter underflows, while the values in the tzpr register and tzsc register are counted alternately (see table 12.10 program- mable waveform generation mode specifications ). a counting starts by counting the value set in the tzpr register. figure 12.23 shows tyzmr and pum registers in this mode. the timer z operates in the same way as the timer y in this mode. see figure 12.17 (timer y operation example in program- mable waveform generation mode ). item specification count source f 1 , f 2 , f 8 , timer y underflow count operation down-count when the timer underflows, it reloads the contents of primary reload register and sec- ondary reload register alternately before continuing counting. output waveform width primary period : (n+1)(m+1)/f i and period secondary period : (n+1)(p+1)/f i period : (n+1){(m+1)+(p+1)}/f i f i : count source frequency n: set value in prez register, m: set value in tzpr register, p: set value in tzsc register count start condition write 1 (count start) to the tzs bit in the tyzmr register count stop condition write 0 (count stop) to the tzs bit in the tyzmr register interrupt request generation timing in half of count source, after timer z underflows during secondary period (at the same time as the tzout output change) [timer z interrupt]. tz out pin function pulse output use timer mode when using this pin as a programmable i/o port. _____ int0 pin functions _______ programmable i/o port, or int0 interrupt input read from timer count value can be read out by reading tzpr register. same applies to prez register (1) . write to timer value written to tzpr register is written to reload register only. same applies to tzsc register and prez register (2) . select function output level latch select function the output level during primary and secondary periods is selected by the tzopl bit. programmable waveform generation output switching function the output from tz out is inverted synchronously when timer z underflows by setting the tzocnt bit in the tyzoc register to 0 . a value in the p3_1 bit is output from the tz out by setting to 1 (3) . notes: 1. even when counting the secondary period, read out the tzpr register. 2. the set value in the tzpr register and tzsc register are made effective by writing a value to the tzpr register. the set values are reflected to the waveform output beginning with the next primary period after writing to the timer z primary register. 3. the tzocntbit is enabled in the following timings when count starts when timer z interrupt request is generated therefore, pulse is output from the next primary period depending on the setting value of the tzocnt bit. table 12.10 programmable waveform generation mode specifications 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 94 of 204 rej09b0062-0120 figure 12.23 tyzmr register and pum register in programmable waveform generation mode bit name f u n c t i o n b i t s y m b o l timer y, z waveform output control register symbol address after reset pum 0084 16 00 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t y o p l t z o p l inoseg i n o s t g i n t 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t t i m e r z o u t p u t l e v e l l a t c h timer y-related bit i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t must set to 0 in programmable waveform generation mode must set to 0 in programmable waveform generation mode 0 : outputs "h" for primary period outputs "l" for secondary period outputs "l" when the timer is stopped 1 : outputs "l" for primary period outputs "h" for secondary period outputs "h" when the timer is stopped ( b 3 - b 0 ) r e s e r v e d b i t must set to 0 r w r w r w rw r w rw 0 0 0 0 0 0 12.3 timer (timer z) t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 b i t n a m e f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t z m o d 1 t y s tywc t y m o d 0 t z m o d 0 timer y-related bit t z w c tzs 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g timer z count start flag timer z operation mode bit b5 b4 timer z write control bit 0 n o t e s : 1 . w h e n t z s b i t = 1 ( s t a r t s c o u n t i n g ) , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o t h e r e l o a d r e g i s t e r o n l y . w h e n t z s b i t = 0 ( s t o p s c o u n t i n g ) , t h e t i m e r y c o u n t v a l u e i s w r i t t e n t o b o t h r e l o a d r e g i s t e r a n d c o u n t e r . r w r w r w r w r w r w r w rw r1edg rw s e t t o " 1 " i n p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e (1 ) 0 1 : p r o g r a m m a b l e w a v e f o r m g e n e r a t i o n m o d e 1 1
r8c/11 group rev.1.20 jan 27, 2006 page 95 of 204 rej09b0062-0120 12.3.3 programmable one-shot generation mode in this mode, upon program command or external trigger input (input to the int0 pin), the microcom- puter outputs the one-shot pulse from the tz out pin (see table 12.11 programmable one-shot generation mode specifications ). when a trigger occurs, the timer starts operating from the point only once for a given period equal to the set value in the tzpr register. the tzsc is unused in this mode. figure 12.24 shows the tyzmr register and pum register in this mode. figure 12.25 shows an operation example in this mode. item specification count source f 1 , f 2 , f 8 , timer y underflow count operation downcounts set value in tzpr register when the timer underflows, it reloads the contents of reload register before completing counting and the tzos bit is 0 . when a count stops, the timer reloads the contents of the reload register before it stops. one-shot pulse output (n+1)(m+1)/fi duration fi : count source frequency, n: set value in prez register, m: set value in tzpr register count start condition set tzos bit in tyzoc register to 1 (start one-shot) (1) input active trigger to int0 pin (2) count stop condition when reloading is completed after count value was set to "00 16 " when tzs bit in tyzmr register is set to 0 (stop counting) when tzos bit in tyzoc register is set to 0 (stop one-shot) interrupt request generation timing in half cycles of count source, after the timer underflows (at the same time as the tzout output ends) [timer z interrupt]. tz out pin function pulse output use timer mode when using this pin as a programmable i/o port. _______ int0 pin function _______ programmable i/o port, int0 interrupt input or external trigger input _______ when the inostg bit in the pum register is set to 0 (int0 one-shot trigger disabled) _______ programmable i/o port or int0 interrupt input _______ when the inostg bit in the pum register is set to 1 (int0 one-shot trigger enabled) _______ external trigger (int0 interrupt input) read from timer count value can be read out by reading tzpr register. same applies to prez register. write to timer value written to tzpr register is written to reload register only (3) . same applies to prez register. select function output level latch select function output level for one-shot pulse waveform is selected by tzopl bit. _______ int0 pin one-shot trigger control function and polarity select function _______ trigger input from int0 pin can be set to active or inactive by inostg bit. also, an active trigger's polarity can be selected by inoseg bit. notes: 1. the tzs bit in the tyzmr register must be set to "1" (start counting). _______ 2. the tzs bit must be set to "1" (start counting), the int0en bit in the inten register to "1" (enabling int0 input), and _____ the inostg bit in the pum register to "1" (enabling int0 one-shot trigger). _______ although the trigger input during counting cannot be acknowledged, the int0 interrupt request is generated. 3. the set values are reflected beginning with the next one-shot pulse after writing to the tzpr register. table 12.11 programmable one-shot generation mode specifications 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 96 of 204 rej09b0062-0120 figure 12.24 tyzmr register and pum register in programmable one-shot generation mode t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 1 6 b i t n a m e f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t z m o d 1 t y s t y w c t y m o d 0 t z m o d 0 t i m e r y - r e l a t e d b i t t z w c tzs 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g t i m e r z c o u n t s t a r t f l a g t i m e r z o p e r a t i o n m o d e b i t b 5 b 4 t i m e r z w r i t e c o n t r o l b i t 1 r w r w r w r w r w r w rw rw r 1 e d g r w set to "1" in programmable one-shot generation mode (1) 0 1 1 0 : p r o g r a m m a b l e o n e - s h o t g e n e r a t i o n m o d e notes: 1. when the tzs bit is set to 1 (count starts), the count value is written to the reload register only. when the tzs bit is set to 0 ( count sto p s ) , the count value is written to both reload re g ister and counter . 12.3 timer (timer z) b i t n a m e function b i t s y m b o l t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t p u m0 0 8 4 1 6 0 0 1 6 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t y o p l tzopl inoseg i n o s t g i n t 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t (1 ) t i m e r z o u t p u t l e v e l l a t c h t i m e r y - r e l a t e d b i t i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t (2 ) reserved bit m u s t s e t t o 0 (b3-b0) rw rw r w r w r w r w 0 0 0 0 0 : e d g e t r i g g e r a t f a l l i n g e d g e 1 : e d g e t r i g g e r a t r i s i n g e d g e 0 : outputs "h" level one-shot pulse. outputs "l" when the timer is stopped. 1 : outputs "l" level one-shot pulse outputs "h" when the timer is stopped. 0 : i n t 0 p i n o n e - s h o t t r i g g e r d i s a b l e d 1 : i n t 0 p i n o n e - s h o t t r i g g e r e n a b l e d (2 ) n o t e s : 1 . t h e i n o s e g b i t i s v a l i d o n l y w h e n t h e i n t 0 p l b i t i n t h e i n t e n r e g i s t e r i s s e t t o " 0 " ( o n e - e d g e ) . 2 . t h e i n o s g t b i t m u s t b e s e t t o 1 a f t e r t h e i n t 0 e n b i t t h e i n o s e g r e g i s t e r a n d t h e i n o s e g b i t i n t h e p u m r e g i s t e r a r e s e t . w h e n s e t t i n g t h e i n o s t g b i t t o " 1 " ( i n t 0 p i n o n e - s h o t t r i g g e r e n a b l e d ) , t h e i n t 0 f 0 a n d i n t 0 f 1 b i t s i n t h e i n t 0 f r e g i s t e r m u s t b e s e t . t h e i n o s t g b i t m u s t b e s e t t o 0 ( i n t 0 p i n o n e - s h o t t r i g g e r d i s a b l e d ) a f t e r t h e t z s b i t i n t h e t y z m r r e g i s t e r i s s e t t o 0 ( c o u n t s t o p ) .
r8c/11 group rev.1.20 jan 27, 2006 page 97 of 204 rej09b0062-0120 figure 12.25 operation example in programmable one-shot generation mode count source tz out pin output ir bit in tzic register tzs bit in tyzmr register 1 0 01 16 00 16 01 16 00 16 timer z primary reload set to 0 when interrupt request is acknowledged or by program waveform output starts waveform output completes tzopl bit in pum register tzos bit in tyzoc register contents of timer z set to 1 by program 01 16 count starts set to 1 by int 0 pin input trigger set to 0 when count completes the above applies to the following conditions; prez=01 16 , tzpr=01 16 tzopl bit in pum register=0, inostg bit= 1(int0 one-shot trigger enabled) inoseg bit= 1(rising edge trigger) int 0 pin input prescaler z underflow signal 1 0 1 0 1 0 0 1 h l set to 1 by program set to 1 by program count starts timer z primary reload waveform output starts waveform output completes 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 98 of 204 rej09b0062-0120 12.3.4 programmable wait one-shot generation mode _______ in this mode, upon program or external trigger input (input to the int0 pin), the microcomputer outputs the one-shot pulse from the tz out pin after waiting for a given length of time (see table 12.12 programmable wait one-shot generation mode specifications ). when a trigger occurs, from this point, the timer starts outputting pulses only once for a given length of time equal to the set value in the tzsc register after waiting for a given length of time equal to the set value in the tzpr register. figure 12.26 shows the tyzmr and pum registers in this mode. figure 12.27 shows an operation example in this mode. item specification count source f 1 , f 2 , f 8 , timer y underflow count operation downcounts set value in timer z primary when a counting of tzpr register underflows, the timer reloads the contents of tzsc register before continuing counting. when a counting of tzsc register underflows, the timer reloads the contents of tzpr register before completing counting and the tzos bit is 0 . when a count stops, the timer reloads the contents of the reload register before it stops. wait time (n+1)(m+1)/fi n: set value in prez register, m: set value in tzpr register one-shot pulse output time (n+1)(p+1)/fi n : set value in prez, p: set value in tzsc register count start condition set tzos bit in tyzoc register to 1 (start one-shot) (1) _______ input active trigger to int0 pin (2) count stop condition when reloading is completed after timer z underflows during secondary period [timer z interrupt] when tzs bit in tyzmr register is set to 0 (stop counting) when tzos bit in tyzoc register is set to 0 (stop one-shot) interrupt request i n half cycles of count source, after count value at counting tzsc register is set "00 16 " generation timing (at the same time as the tzout output change) [timer z interrupt] tz out pin function pulse output use timer mode when using this pin as a programmable i/o port. _______ int0 pin function _______ programmable i/o port, int0 interrupt input or external trigger input _______ when the inostg bit in the pum register is set to 0 (int0 one-shot trigger disabled) _______ programmable i/o port or int0 interrupt input _______ when the inostg bit in the pum register is set to 1 (int0 one-shot trigger enabled) _______ external trigger (int0 interrupt input) read from timer count value can be read out by reading tzpr register. same applies to prez register. write to timer value written to tzpr register and prez register are written to reload register only (3) . same applies to tzsc register. select function output level latch select function output level for one-shot pulse waveform is selected by tzopl bit. _______ int0 pin one-shot trigger control function and polarity select function _______ trigger input from int0 pin can be set to active or inactive by inostg bit. also, an active trigger's polarity can be selected by inoseg bit. notes: 1. the tzs bit in the tyzmr register must be set to "1" (start counting). _______ 2. the tzs bit must be set to "1" (start counting), the int0en bit in the inten register to "1" (enabling int0 input), and _____ the inostg bit in the pum register to "1" (enabling int0 one-shot trigger). _______ although the trigger input during counting cannot be acknowledged, the int0 interrupt request is generated. 3. the set values are reflected beginning with the next one-shot pulse after writing to the tzpr register. table 12.12 programmable wait one-shot generation mode specifications 12.3 timer (timer z)
r8c/11 group rev.1.20 jan 27, 2006 page 99 of 204 rej09b0062-0120 figure 12.26 tyzmr register and pum register in programmable wait one-shot generation mode 12.3 timer (timer z) t i m e r y , z m o d e r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t t y z m r0 0 8 0 1 6 0 0 2 b i t n a m e f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 tzmod1 tys t y w c t y m o d 0 tzmod0 timer y-related bit t z w c tzs 0 : stops counting 1 : starts counting timer z count start flag timer z operation mode bit b 5 b 4 timer z write control bit 1 n o t e s : 1 . w h e n t h e t z s b i t i s s e t t o " 0 " ( s t o p c o u n t i n g ) , t h e t i m e r r e l o a d s t h e c o n t e n t o f t h e r e l o a d r e g i s t e r b e f o r e i t s t o p s . r e a d o u t t h e c o u n t v a l u e b e f o r e y o u s t o p t h e t i m e r . r w r w r w r w r w r w r w r w r1edg rw m u s t s e t t o " 1 " i n p r o g r a m m a b l e w a i t o n e - s h o t g e n e r a t i o n m o d e 1 1 1 1 : programmable wait one-shot generation mode bit name function b i t s y m b o l t i m e r y , z w a v e f o r m o u t p u t c o n t r o l r e g i s t e r s y m b o la d d r e s sa f t e r r e s e t p u m0 0 8 4 1 6 0 0 1 6 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t y o p l tzopl i n o s e g i n o s t g i n t 0 p i n o n e - s h o t t r i g g e r p o l a r i t y s e l e c t b i t (1 ) t i m e r z o u t p u t l e v e l l a t c h t i m e r y - r e l a t e d b i t i n t 0 p i n o n e - s h o t t r i g g e r c o n t r o l b i t (2 ) r e s e r v e d b i t must set to 0 (b3-b0) r w r w r w r w r w r w 0 0 0 0 0 : edge trigger at falling edge 1 : edge trigger at rising edge 0 : outputs "h" level one-shot pulse. outputs "l" when the timer is stopped. 1 : outputs "l" level one-shot pulse outputs "h" when the timer is stopped. 0 : i n t 0 p i n o n e - s h o t t r i g g e r d i s a b l e d 1 : i n t 0 p i n o n e - s h o t t r i g g e r e n a b l e d (2 ) n o t e s : 1 . t h e i n o s e g b i t i s v a l i d o n l y w h e n t h e i n t 0 p l b i t i n t h e i n t e n r e g i s t e r i s s e t t o " 0 " ( o n e - e d g e ) . 2 . t h e i n o s g t b i t m u s t b e s e t t o 1 a f t e r t h e i n t 0 e n b i t t h e i n o s e g r e g i s t e r a n d t h e i n o s e g b i t i n t h e p u m r e g i s t e r a r e s e t . w h e n s e t t i n g t h e i n o s t g b i t t o " 1 " ( i n t 0 p i n o n e - s h o t t r i g g e r e n a b l e d ) , t h e i n t 0 f 0 a n d i n t 0 f 1 b i t s i n t h e i n t 0 f r e g i s t e r m u s t b e s e t . t h e i n o s t g b i t m u s t b e s e t t o 0 ( i n t 0 p i n o n e - s h o t t r i g g e r d i s a b l e d ) a f t e r t h e t z s b i t i n t h e t y z m r r e g i s t e r i s s e t t o 0 ( c o u n t s t o p ) .
r8c/11 group rev.1.20 jan 27, 2006 page 100 of 204 rej09b0062-0120 t z o u t p i n o u t p u t t h e a b o v e a p p l i e s t o t h e f o l l o w i n g c o n d i t i o n s ; p r e z = 0 1 1 6 , t z p r = 0 1 1 6 , t z s c = 0 2 1 6 t z o p l b i t i n p u m r e g i s t e r = 0 , i n o s t g b i t = 1 ( i n t 0 o n e - s h o t t r i g g e r e n a b l e d ) i n o s e g b i t = 1 ( r i s i n g e d g e t r i g g e r ) ir bit in tzic register 0 1 1 6 0 0 1 6 02 16 w a i t starts t z o p l b i t i n p u m r e g i s t e r int 0 input pin c o n t e n t s o f t i m e r z t z s b i t i n t y z m r r e g i s t e r 1 0 0 1 1 6 0 1 1 6 0 0 1 6 ti mer z secondary reload c o u n t s o u r c e p r e s c a l e r z u n d e r f l o w s i g n a l tzos bit in tyzoc register set to 1 by program or 1 by int 0 pin input trigger 1 0 1 0 1 0 1 0 h l set to 1 by program set to 0 when count completes c ount starts ti mer z primary reload set to 0 when interrupt request is acknowledged or by program s e t t o 0 b y p r o g r a m w ave f orm output starts w ave f orm output completes figure 12.27 operation example in programmable wait one-shot generation mode 12.3 timer (timer z)
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 101 of 204 rej09b0062-0120 12.4 timer c timer c is a 16-bit timer. figure 12.28 shows a block diagram of timer c. figure 12.29 shows a block diagram of cmp waveform generation unit. figure 12.30 shows a block diagram of cmp waveform output unit. the timer c has two modes: input capture mode and output compare mode. figures 12.31 shows tc, tm0, tm1, and tcc0 registers. figure 12.32 shows tcc1 and tcout regis- ters. figure 12.28 timer c block diagram compare 0 interrupt transfer signal f ring128 capture and compare 0 register upper 8 bits lower 8 bits tm0 register compare circuit 0 counter upper 8 bits lower 8 bits tc register data bus compare register 1 upper 8 bits lower 8 bits tm1 register =11 2 f 1 f 8 f 32 f ring -fast compare circuit 1 timer c interrupt timer c counter reset signal =10 2 =01 2 =00 2 compare 1 interrupt int 3 /tc in tcc11 to tcc10 f 1 f 8 f 32 =01 2 =10 2 =11 2 edge detection tcc07=0 tcc07=1 digital filter int3 interrupt tcc12 =0 tcc12 =1 =00 2 other than 00 2 tcc02 to tcc01 tcc00 tcc01 to tcc02, tcc07: bits in tcc0 register tcc10 to tcc12: bits in tcc1 register sampling clock
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 102 of 204 rej09b0062-0120 figure 12.29 cmp waveform generation unit figure 12.30 cmp waveform output unit compare 1 interrupt signal h l latch t dq reverse reverse l h cmp output (internal signal) compare 0 interrupt signal =10 2 =01 2 tcc15 to tcc14 =01 2 =10 2 =11 2 tcc17 to tcc16 =11 2 tcc17 tcc16 tcc15 tcc14 tcc14 to tcc17: bits in tcc1 re g ister r reset c m p o u t p u t ( i n t e r n a l s i g n a l ) c m p 0 0 p d 1 _ 0 tcout0=1 t c o u t 0 = 0 t c o u t 0 p 1 _ 0 t c o u t 6 = 1 t c o u t 6 = 0 inverted t h i s d i a g r a m i s a b l o c k d i a g r a m o f t h e c m p 0 0 w a v e f o r m o u t p u t u n i t . t h e c m p 0 1 t o c m p 0 2 a n d c m p 1 0 t o c m p 1 2 w a v e f o r m o u t p u t u n i t s a r e t h e s a m e c o n f i g u r a t i o n s . r e g i s t e r b i t s e t t i n g v a l u e t c o u t t c o u t 0 1 1 1 1 p 1 p 1 _ 0 1 1 0 0 t c o u t t c o u t 6 0 1 0 1 cmp0 0 waveform output cmp0 0 reversed waveform output l output h output c m p 0 0 o u t p u t
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 103 of 204 rej09b0062-0120 figure 12.31 tc register, tm0 register, tm1 register, tcc0 register s y m b o la d d r e s sa f t e r r e s e t t c0 0 9 1 1 6 - 0 0 9 0 1 6 0 0 0 0 1 6 rw i n t e r n a l c o u n t s o u r c e i s c o u n t e d " 0 0 0 1 6 " c a n b e r e a d o u t b y r e a d i n g w h e n t c c 0 0 b i t = 0 ( s t o p s c o u n t i n g ) c o u n t v a l u e c a n b e r e a d o u t b y r e a d i n g w h e n t c c 0 0 b i t = 1 ( s t a r t c o u n t i n g ) f u n c t i o n t i m e r c r e g i s t e r c a p t u r e a n d c o m p a r e 0 r e g i s t e r b 7 b 0 b 7 b 0 ( b 1 5 ) ( b 8 ) (b 15 ) ( b 8 ) ro symbol address after reset tm1 009f 16 -009e 16 ffff 16 function c o m p a r e 1 r e g i s t e r b 7 b 0 b 7 b 0 (b 15 ) (b 8 ) rw r w t h e v a l u e c o m p a r e d w i t h t i m e r c i s s t o r e d mode output compare mode symbol address after reset tm0 009d 16 -009c 16 0000 16 2 when active edge of measurement pulse is input, the value of the tc register is stored f u n c t i o n b 7 b 0 b 7 b 0 r w ro the value compared with timer c is stored m o d e i n p u t c a p t u r e m o d e output compare mode (1) mode f u n c t i o n rw rw setting range 0 0 0 0 1 6 t o f f f f 1 6 setting range 0000 16 to ffff 16 n o t e s : 1 . w h e n s e t t i n g a v a l u e i n t h e t m 0 r e g i s t e r , s e t t h e t c c 1 3 b i t i n t h e t c c 1 r e g i s t e r t o 1 ( c o m p a r e 0 o u t p u t s e l e c t e d ) w h e n t h e t c c 1 3 b i t i s s e t t o 0 ( c a p t u r e s e l e c t e d ) , t h e v a l u e c a n n o t b e w r i t t e n . 2 . w h e n t h e t c c 1 3 b i t i n t h e t c c 1 r e g i s t e r i s s e t t o 1 , t h e v a l u e i s s e t t o f f f f 1 6 . t i m e r c c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sa f t e r r e s e t t c c 00 0 9 a 1 6 0 0 1 6 b i t n a m e f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f r i n g - f a s t t c c 0 4 t c c 0 2 t c c 0 1 t c c 0 0 t c c 0 3 timer c count start bit timer c count source select bit (1) 0 : c o u n t s t o p 1 : c o u n t s t a r t t c c 0 7 b 2 b 1 0 0 : r i s i n g e d g e 0 1 : f a l l i n g e d g e 1 0 : b o t h e d g e s 1 1 : a v o i d t h i s s e t t i n g b4 b3 r w ( b 6 - b 5 ) int3 interrupt and capture polarity select bit (1, 2) int3 interrupt and capture input switching bit (1, 2) 0 : int3 1 : f ring128 r w rw rw r w n o t e s : 1 . c h a n g e t h i s b i t w h e n t c c 0 0 b i t i s s e t t o 0 ( c o u n t s t o p ) . 2 . t h e i r b i t i n t h e i n t 3 i c m a y b e s e t t o 1 ( i n t e r r u p t r e q u e s t e d ) w h e n t h e t c c 0 3 , t c c 0 4 , o r t c c 0 7 b i t i s r e w r i t t e n . r e f e r t o t h e p a r a g r a p h 1 9 . 2 . 5 c h a n g i n g i n t e r r u p t f a c t o r i n t h e u s a g e n o t e s r e f e r e n c e b o o k . rw rw r e s e r v e d b i t set to "0" rw 0 0
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 104 of 204 rej09b0062-0120 figure 12.32 tcc1 register and tcout register t i m e r c c o n t r o l r e g i s t e r 1 symbol address after reset tcc1 009b 16 00 16 b i t n a m e function bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t c c 1 1 t c c 1 0 b1 b0 i n t 3 i n p u t f i l t e r s e l e c t b i t (1 ) timer c counter reload select bit (3) t c c 1 2 rw r w r w r w 0 0 : n o f i l t e r 0 1 : f i l t e r w i t h f 1 s a m p l i n g 1 0 : f i l t e r w i t h f 8 s a m p l i n g 1 1 : f i l t e r w i t h f 3 2 s a m p l i n g 0 : n o r e l o a d ( f r e e - r u n ) 1 : s e t t c r e g i s t e r t o 0 0 0 0 1 6 a t c o m p a r e 1 m a t c h notes: 1. input is recognized only when the same value from int3 pin is sampled three times in succession. 2. the tcc00 bit in the tcc0 register should be set to 0 (count stop) when rewriting the tcc13 bit. 3. the tcc12 and tcc14 to tcc17 should be set to 0 when the tcc13 bit is 0 (input capture mode). c o m p a r e 0 / c a p t u r e s e l e c t b i t (2 ) t c c 1 3 r w 0 : c a p t u r e ( i n p u t c a p t u r e m o d e ) (3 ) 1 : c o m p a r e 0 o u t p u t ( o u t p u t c o m p a r e m o d e ) c o m p a r e 0 o u t p u t m o d e s e l e c t b i t (3 ) t c c 1 4 r w 0 0 : c m p o u t p u t r e m a i n s u n c h a n g e d e v e n w h e n c o m p a r e 0 s i g n a l m a t c h e d 0 1 : c m p o u t p u t i s r e v e r s e d w h e n c o m p a r e 0 s i g n a l i s m a t c h e d 1 0 : c m p o u t p u t i s s e t t o l o w w h e n c o m p a r e 0 s i g n a l i s m a t c h e d 1 1 : c m p o u t p u t i s s e t t o h i g h w h e n c o m p a r e 0 s i g n a l i s m a t c h e d b5 b4 c o m p a r e 1 o u t p u t m o d e s e l e c t b i t (3 ) t c c 1 6 r w 0 0: cmp output remains unchanged even when compare 1 signal matched 0 1: cmp output is reversed when compare 1 signal is matched 1 0: cmp output is set to low when compare 1 signal is matched 1 1: cmp output is set to high when compare 1 signal is matched b 7 b 6 t c c 1 5 tcc17 t i m e r c o u t p u t c o n t r o l r e g i s t e r (1 ) symbol address after reset tcout 00ff 16 00 16 b i t n a m e f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t c o u t 1 t c o u t 0 cmp output enable bit 0 r w r w r w 0: disable cmp output from cmp0 0 1: enable cmp output from cmp0 0 n o t e s : 1 . s e t t h e b i t s w h i c h a r e n o t u s e d f o r t h e c m p o u t p u t t o 0 . cmp output enable bit 2 t c o u t 4 r w t c o u t 6 rw t c o u t 5 c m p o u t p u t e n a b l e b i t 1 0: disabe cmp output from cmp0 1 1: enable cmp output from cmp0 1 0 : d i s a b l e c m p o u t p u t f r o m c m p 0 2 1 : e n a b l e c m p o u t p u t f r o m c m p 0 2 c m p o u t p u t r e v e r s e b i t 0 0: not reverse cmp output from cmp1 0 to cmp1 2 1: reverse cmp output from cmp1 0 to cmp1 2 c m p o u t p u t r e v e r s e b i t 1 r w t c o u t 2 r w t c o u t 3 c m p o u t p u t e n a b l e b i t 3 0 : d i s a b l e c m p o u t p u t f r o m c m p 1 0 1 : e n a b l e c m p o u t p u t f r o m c m p 1 0 r w c m p o u t p u t e n a b l e b i t 4 0 : d i s a b l e c m p o u t p u t f r o m c m p 1 1 1 : e n a b l e c m p o u t p u t f r o m c m p 1 1 c m p o u t p u t e n a b l e b i t 5 0 : d i s a b l e c m p o u t p u t f r o m c m p 1 2 1 : e n a b l e c m p o u t p u t f r o m c m p 1 2 r w 0 : n o t r e v e r s e c m p o u t p u t f r o m c m p 0 0 t o c m p 0 2 1 : r e v e r s e c m p o u t p u t f r o m c m p 0 0 t o c m p 0 2 tcout7
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 105 of 204 rej09b0062-0120 12.4.1 input capture mode this mode uses an edge input to tc in pin or the f ring128 clock as trigger to latch the timer value and generates an interrupt request. the tc in input has a digital filter and this prevents an error caused by noise or so on from occurring. table 12.13 shows specifications in input capture mode. figure 12.33 shows an operation example of input capture mode. item specification count source f 1 , f 8 , f 32 , f ring-fast count operation count up transfer value in tc register to tm0 register at active edge of measurement pulse value in tc register is set to 0000 16 when a counting stops count start condition tcc00 bit in tcc0 register is set to 1 (count start) count stop condition tcc00 bit in tcc0 register is set to 0 (count stop) i nterrupt request _____ when active edge of measurement pulse is input [int3 interrupt] (2) generation timing when timer c overflows [timer c interrupt] ______ int3/tc in pin function _______ programmable i/o port or measurement pulse input (int3 interrupt input) p10 to p12, p33 to p35 programmable i/o port pin function counter value reset timing when tcc00 bit in tcc0 register is set to 0 (capture disabled) read from timer (1) count value can be read out by reading tc register. count value at measurement pulse active edge input can be read out by reading tm0 register. write to timer write to tc register and tm0 register is disabled select function _____ int3/tc in polarity select function measurement pulse active edge is selected by tcc03 to tcc04 bits digital filter function digital filter sampling frequency is selected by tcc11 to tcc10 bits trigger select function tc in input or f ring128 is selected by tcc07 bit. notes: 1. tc register and tm0 register must be read in 16-bit units. _______ 2. the int3 interrupt is acknowledged by digital filter delay and one count source cycle delay (max.) table 12.13 input capture mode specifications
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 106 of 204 rej09b0062-0120 counter contents (hex) tcc00 bit in tcc0 register measurement pulse (tc in pin input) tm0 register ffff 16 0000 16 count start ir bit in tcic register h l 1 0 set to 0 when interrupt request is accepted, or set by program set to "0" by program set to "1" by program overflow measurement value 2 indeterminate set to 0 when interrupt request is accepted, or set by program ir bit in int3ic register measurement value 1 transmit timing from timer c counter to tm0 register measurement value 1 measurement value 2 measurement value 3 indeterminate transmit (measurement value 3) transmit (measurement value 2) transmit (measurement value 1) time measure- ment value 3 1 0 1 0 the delay caused by digital filter and one count source cycle delay(max.) conditions: tcc0 register tcc04 to tcc03 bits=01 2 (capture input polarity is set for falling edge), tcc07=0 (int3/tc in input as capture input trigger) figure 12.33 operation example of timer c in input capture mode
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 107 of 204 rej09b0062-0120 12.4.2 output compare mode in this mode, an interrupt request is generated when the value of tc register matches the value of tm0 or tm1 register. table 12.14 shows specifications in output compare mode. figure 12.34 shows an operation example of output compare mode. item specification count source f 1 , f 8 , f 32 , f ring -fast count operation count up value in tc register is set to 0000 16 when a counting stops count start condition tcc00 bit in tcc0 register is set to 1 (count start) count stop condition tcc00 bit in tcc0 register is set to 0 (count stop) waveform output start when 1 (cmp output enabled) is written to tcout0 to tcout5 bits. (2) condition waveform output stop when 0 (cmp output disabled) is written to tcout0 to tcout5 bits. condition i nterrupt request when a match occurs in compare circuit 0 [compare 0 interrupt] generation timing when a match occurs in compare circuit 1 [compare 1 interrupt] when time c overflows [timer c interrupt] ______ int3/tc in pin function _______ programmable i/o port or int3 interrupt input p1 0 to p1 2 pins and p3 0 to programmable i/o port or cmp output (2) p3 2 pins function counter value reset timing when tcc00 bit in tcc0 register is set to 0 (count stop) read from timer (1) value in compare register can be read out by reading tm0 register and tm1 register. count value can be read out by reading tc register. write to timer (1) write to tc register is disabled. values written to tm0 register and tm1 register are stored in compare register at the following timings: - when tm0 and tm1 registers are written if tcc00 bit is 0 (count stop) - when counter overflows if tcc00 bit is 1 (in counting) and tcc12 bit in tcc1 register is 0 (free-run) - when compare 1 matches counter if tcc00 bit is 1 and tcc12 bit is 1 (set tc register to 0000 16 at compare 1 match) select function timer c counter reload select function counter value in tc register at match occurrence in compare circuit 1 is set or not set to 0000 16 selected by tcc12 bit in tcc1 register. output level at match occurrence in compare circuit 0 can be selected by tcc15 to tcc14 bits in tcc1 register. similarly, output level at match occurrence in compare circuit 1 can be selected by tcc17 to tcc16 bits in tcc1 register. whether output is reversed or not can be selected by tcout6 to tcout7 bits in tcout register. notes: 1. tc, tm0, and tm1 registers should be accessed in 16-bit units. 2. when the corresponding port data is 1 , the waveform is output depending on the setting of the registers tcc1 and tcout. when the corresponding port data is 0 , the fixed level is output (refer to figure 12.30 cmp waveform output unit. table 12.14 output compare mode specifications
r8c/11 group 12.4 timer (timer c) rev.1.20 jan 27, 2006 page 108 of 204 rej09b0062-0120 figure 12.34 operation example of timer c in output compare mode s e t v a l u e i n t m 1 r e g i s t e r 0 0 0 0 1 6 t i m e t c c 0 0 b i t i n t c c 0 r e g i s t e r i r b i t i n c m p 0 i c r e g i s t e r c o u n t e r c o n t e n t ( h e x ) s e t t o 1 b y p r o g r a m c o u n t s t a r t ir bit in cmp1ic register s e t t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r s e t b y p r o g r a m the above applies to the following conditions. tcc12 bit in tcc1 register=1 (tc register is set to 0000 16 at compare 1 match occurrence ) tcc13 bit in tcc1 register=1 (compare 0 output selected) tcc15 to tcc14 bits in tcc1 register =11 2 (cmp output level is set to high at compare 0 match occurrence)tcc17 to tcc16 bits in tcc1 register=10 2 (cmp output level is set to low at compare 1 match occurrence) tcout6 bit in tcout register=0 (not reversed) tcout7 bit in tcout register =1 (reversed) tcout0 bit in tcout register=1 (cmp0 0 output enabled) tcout3 bit in tcout register=1 (cmp1 0 output enabled) p1_0 bit in p1 register=1 (high) p3_0 bit in p3 register=1 (high) s e t t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r s e t b y p r o g r a m s e t v a l u e i n t m 0 r e g i s t e r cmp0 0 output 1 0 c m p 1 0 o u t p u t match m a t c h m a t c h 1 0 1 0 1 0 1 0
r8c/11 group 13. serial interface rev.1.20 jan 27, 2006 page 109 of 204 rej09b0062-0120 13. serial interface serial interface is configured with two channels: uart0 to uart1. uart0 and uart1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 13.1 shows a block diagram of uarti (i=0, 1). figure 13.2 shows a block diagram of the uarti transmit/receive. uart0 has two modes: clock synchronous serial i/o mode, and clock asynchronous serial i/o mode (uart mode). uart1 has only one mode, clock asynchronous serial i/o mode (uart mode). figures 13.3 to 13.5 show the uarti-related registers. figure 13.1 uarti (i=0, 1) block diagram internal external main clock or on-chip oscillator clock receive clock transmit clock f 1sio 1/8 f 8sio 1/4 f 32sio 1/2 clk 1 to clk 0 =00 2 =01 2 =10 2 ckdir=0 ckdir=1 clk 0 (uart0) rxd 0 f 1sio 1/(n0+1) txd 0 rxd 1 clk 1 to clk 0 =00 2 =01 2 =10 2 to p0 0 txd 10 txd 11 txd1sel=1 txd1sel=0 txd1en 1/(n1+1) (uart1) 1/16 1/16 1/16 1/16 u0brg register f 8sio f 32sio f 1sio f 8sio f 32sio clk polarity reversing circuit clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) reception control circuit transmission control circuit transmit/ receive unit uart reception u1brg register internal uart transmission reception control circuit transmission control circuit transmit/ receive unit reception control circuit transmission control circuit
r8c/11 group 13. serial interface rev.1.20 jan 27, 2006 page 110 of 204 rej09b0062-0120 i=0, 1 sp: stop bit par: parity bit s p s p par 2sp 1 s p u a r t u a r t ( 7 b i t s ) u a r t ( 8 b i t s ) uart (7 bits) uart (9 bits) c l o c k s y n c h r o n o u s t y p e c l o c k s y n c h r o n o u s t y p e txdi u a r t i t r a n s m i t r e g i s t e r p a r e n a b l e d p a r d i s a b l e d d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 u i t b r e g i s t e r msb/lsb conversion circuit u a r t ( 8 b i t s ) u a r t ( 9 b i t s ) c l o c k s y n c h r o n o u s t y p e uirb register u a r t i r e c e i v e r e g i s t e r 2 s p 1 s p par enabled p a r d i s a b l e d u a r t u a r t ( 7 b i t s ) uart ( 9 bi ts ) c l o c k s y n c h r o n o u s t y p e clock synchronous type uart (7 bits) uart (8 bits) r x d i clock synchronous type uart (8 bits) uart (9 bits) data bus low-order bits m s b / l s b c o n v e r s i o n c i r c u i t d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 s ps p p a r 0 data bus high-order bits n o t e s : 1 . c l o c k s y n c h r o n o u s t y p e i s p r o v i d e i n u a r t 0 o n l y . p r y e = 1 prye=0 prye=0 p r y e = 1 figure 13.2 uarti transmit/receive unit
r8c/11 group 13. serial interface rev.1.20 jan 27, 2006 page 111 of 204 rej09b0062-0120 figure 13.3 u0tb and u1tb registers, u0rb and u1rb registers, and u0brg and u1brg registers b 7 ( b 1 5 ) ( b 1 5 ) symbol address after reset u0rb 00a7 16 -00a6 16 indeterminate u1rb 00af 16 -00ae 16 indeterminate b 7 b 0 ( b 8 ) b 7 b 0 u a r t i r e c e i v e b u f f e r r e g i s t e r ( 1 ) ( i = 0 , 1 ) f u n c t i o n b i t n a m e b i t s y m b o l 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found n o t e s : 1 . r e a d o u t t h e u i r b r e g i s t e r i n 1 6 - b i t u n i t . 2 . a l l o f t h e s u m , p e r , f e r a n d o e r b i t s a r e s e t t o 0 ( n o e r r o r ) w h e n t h e s m d 2 t o s m d 0 b i t s i n t h e u i m r r e g i s t e r a r e s e t t o 0 0 0 2 ( s e r i a l i n t e r f a c e d i s a b l e d ) o r t h e r e b i t i n t h e u i c 1 r e g i s t e r i s s e t t o 0 ( r e c e p t i o n d i s a b l e d ) . t h e s u m b i t i s s e t t o 0 ( n o e r r o r ) w h e n a l l o f t h e p e r , f e r a n d o e r b i t s a r e s e t t o 0 ( n o e r r o r ) . t h e p e r a n d f e r b i t s a r e s e t t o 0 e v e n w h e n t h e h i g h e r b y t e o f t h e u i r b r e g i s t e r i s r e a d . o e r f e r p e r sum overrun error flag (2) framing error flag (2) 4!),.:; ? error sum flag (2) 0 : no overrun error 1 : overrun error found receive data (d 7 to d 0 ) uarti bit rate register (1, 2, 3) (i=0, 1) b 0 symbol address after reset u0brg 00a1 16 indeterminate u1brg 00a9 16 indeterminate f u n c t i o n assuming that set value = n, uibrg divides the count source by n + 1 0 0 1 6 t o f f 1 6 s e t t i n g r a n g e notes: 1. write to this register while serial interface is neither transmitting nor receiving. 2. use mov instruction to write to this register. 3. after setting the clk0 to clk1 bits of the uic0 register, write to the uibrg register. b 7 b 0 ( b 8 ) b 7 b 0 u a r t i t r a n s m i t b u f f e r r e g i s t e r ( 1 , 2 ) ( i = 0 , 1 ) f u n c t i o n t r a n s m i t d a t a n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e . s y m b o la d d r e s sa f t e r r e s e t u 0 t b0 0 a 3 1 6 - 0 0 a 2 1 6 i n d e t e r m i n a t e u 1 t b0 0 a b 1 6 - 0 0 a a 1 6 i n d e t e r m i n a t e r w notes: 1. when transfer data length is 9-bit long, write high-byte first then low-byte. 2. use mov instruction to write to this register. w o r w ro r o ro ro ro ( b 7 - b 0 ) ( b 1 1 - b 9 ) r w wo r e c e i v e d a t a ( d 8 ) r o (b8) n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e . b i t s y m b o l ( b 8 - b 0 ) ( b 1 5 - 6 9 )
r8c/11 group 13. serial interface rev.1.20 jan 27, 2006 page 112 of 204 rej09b0062-0120 u a r t i t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( i = 0 , 1 ) s y m b o la d d r e s sa f t e r r e s e t u 0 m r0 0 a 0 1 6 0 0 1 6 u 1 m r0 0 a 8 1 6 0 0 1 6 b 7b 6b 5b4b 3b2b 1b 0 bit name b i t s y m b o l rw c k d i r s m d 1 smd0 serial interface mode select bit (2) s m d 2 i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t (3 ) s t p s p r y p r y e (b7) parity enable bit 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k (1 ) s t o p b i t l e n g t h s e l e c t b i t o d d / e v e n p a r i t y s e l e c t b i t r e s e r v e d b i t 0 : 1 stop bit 1 : 2 stop bits 0 : parity disabled 1 : parity enabled 0 0 0 : s e r i a l i n t e r f a c e d i s a b l e d 0 0 1 : c l o c k s y n c h r o n o u s s e r i a l i / o m o d e 1 0 0 : u a r t m o d e t r a n s f e r d a t a 7 b i t s l o n g 1 0 1 : u a r t m o d e t r a n s f e r d a t a 8 b i t s l o n g 1 1 0 : u a r t m o d e t r a n s f e r d a t a 9 b i t s l o n g d o n o t s e t e x c e p t a b o v e b2 b1 b0 effective when prye = 1 0 : odd parity 1 : even parity s e t t o 0 f u n c t i o n n o t e s : 1 . m u s t s e t t h e p 1 _ 6 b i t i n t h e p d 1 r e g i s t e r t o 0 ( i n p u t ) . 2 . f o r t h e u 1 m r r e g i s t e r , t h e s m d 2 t o s m d 0 b i t s m u s t n o t b e s e t e x c e p t t h e f o l l o w i n g s : 0 0 0 2 , 1 0 0 2 , 1 0 1 2 , o r 1 1 0 2 . 3 . m u s t s e t t h e c k d i r b i t t o 0 ( i n t e r n a l c l o c k ) i n u a r t 1 . uarti transmit/receive control register 0 (i=0, 1) s y m b o la d d r e s sa f t e r r e s e t u 0 c 00 0 a 4 1 6 0 8 1 6 u 1 c 00 0 a c 1 6 0 8 1 6 b7 b6 b5 b4 b3 b2 b1 b0 function t x e p t c l k 1 c l k 0 (b2) n c h c k p o l b r g c o u n t s o u r c e s e l e c t b i t ( 1 ) t r a n s m i t r e g i s t e r e m p t y f l a g 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge c l k p o l a r i t y s e l e c t b i t d a t a o u t p u t s e l e c t b i t 0 0 : f 1sio is selected 0 1 : f 8sio is selected 1 0 : f 32sio is selected 1 1 : avoid this setting b1 b0 0 : lsb first 1 : msb first 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e . 0 : t x d i p i n i s a p i n o f c m o s o u t p u t 1 : t x d i p i n i s a p i n o f n - c h a n n e l o p e n - d r a i n o u t p u t u f o r mt r a n s f e r f o r m a t s e l e c t b i t bit name bit symbol rw rw rw rw rw r w rw rw r w rw rw rw rw rw r w r o 0 0 r e s e r v e d b i t set to 0 ( b 4 ) n o t e s : 1 . i f t h e b r g c o u n t s o u r c e i s s w i t c h e d , s e t t h e u i b r g r e g i s t e r a g a i n . figure 13.4 u0mr and u1mr registers and u0c0 and u1c0 registers
r8c/11 group 13. serial interface rev.1.20 jan 27, 2006 page 113 of 204 rej09b0062-0120 u a r t i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( i = 0 , 1 ) symbol address after reset u0c1 00a5 16 02 16 u1c1 00ad 16 02 16 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e bit symbol r w function t e t i r e r i t r a n s m i t e n a b l e b i t r e c e i v e e n a b l e b i t (1 ) r e c e i v e c o m p l e t e f l a g (2 ) t r a n s m i t b u f f e r e m p t y f l a g 0 : transmission disabled 1 : transmission enabled 0 : data present in uitb register 1 : no data present in uitb register 0 : reception disabled 1 : reception enabled 0 : no data present in uirb register 1 : data present in uirb register n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t 0 . w h e n r e a d , i t s c o n t e n t i s 0 . r w r w r o r o ( b 7 - b 4 ) n o t e s : 1 . a s f o r t h e u a r t 1 , s e t t h e t x d 1 e n b i t i n t h e u c o n r e g i s t e r b e f o r e s e t t i n g t h i s b i t t o r e c e p t i o n e n a b l e d . 2 . t h e r i b i t i s s e t t o " 0 " w h e n t h e h i g h e r b y t e o f t h e u i r b r e g i s t e r i s r e a d . figure 13.5 u0c1 and u1c1 registers and ucon register n o t e s : 1 . f o r p 3 7 , s e l e c t 0 ( r x d 1 ) f o r d a t a r e c e i v e , a n d 1 ( t x d 1 0 ) f o r d a t a t r a n s f e r . s e t t h e p d 3 _ 7 b i t i n t h e p d 3 r e g i s t e r t o 0 ( i n p u t m o d e ) w h e n r e c e i v i n g . 2 . d o n o t s e t t h e t x d 1 s e l a n d t x d 1 e n b i t s t o 1 a t t h e s a m e t i m e s i n c e t h e y f u n c t i o n i n d e p e n d e n t l y . uart transmit/receive control register 2 s y m b o la d d r e s sa f t e r r e s e t u c o n0 0 b 0 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 bit name b i t s y m b o l rw f u n c t i o n t x d 1 s e l t x d 1 e n uart0 transmit interrupt cause select bit u a r t 0 c o n t i n u o u s r e c e i v e m o d e e n a b l e b i t 0 : c o n t i n u o u s r e c e i v e m o d e d i s a b l e d 1 : c o n t i n u o u s r e c e i v e m o d e e n a b l e p o r t t x d 1 1 s w i t c h i n g b i t ( 2 ) u a r t 1 t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : t r a n s m i t b u f f e r e m p t y ( t l = 1 ) 1 : t r a n s m i s s i o n c o m p l e t e d ( t x e p t = 1 ) 0 : r x d 1 1 : t x d 1 0 n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t 0 . w h e n r e a d , i t s c o n t e n t i s 0 . u0irs u 1 i r s u 0 r r m t x d 1 0 / r x d 1 s e l e c t b i t ( 1 , 2 ) 0 : i / o p o r t p 0 0 1 : t x d 1 1 must set to 0 r w rw r w r w r w r w (b7) (b4-b3) r e s e r v e d b i t 0 0
r8c/11 group 13.1 clock synchronous serial i/o mode rev.1.20 jan 27, 2006 page 114 of 204 rej09b0062-0120 13.1 clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. this mode can be selected with uart0. table 13.1 lists the specifications of the clock synchronous serial i/o mode. table 13.2 lists the registers used in clock synchronous serial i/o mode and the register values set. item specification transfer data format transfer data length: 8 bits transfer clock ckdir bit in u0mr register is set to 0 (internal clock): fi/(2(n+1)) fi=f 1sio , f 8sio , f 32sio n=setting value in uibrg register: 00 16 to ff 16 ckdir bit is set to 1 (external clock ): input from clk0 pin transmission start condition before transmission can start, the following requirements must be met (1) _ te bit in u0c1 register is set to 1 (transmission enabled) _ ti bit in u0c1 register is set to 0 (data present in u0tb register) reception start condition before reception can start, the following requirements must be met (1) _ re bit in u0c1 register is set to 1 (reception enabled) _ te bit in u0c1 register is set to 1 (transmission enabled) _ ti bit in u0c1 register is set to 0 (data present in the u0tb register) for transmission, one of the following conditions can be selected _ u0irs bit is set to 0 (transmit buffer empty): when transferring data from u0tb register to uart0 transmit register (at start of transmission) _ u0irs bit is set to 1 (transfer completed): when serial interface finished sending data from uarti transmit register for reception when transferring data from the uart0 receive register to the u0rb register (at completion of reception) error detection overrun error (2) this error occurs if serial interface started receiving the next data before reading the u0rb register and received the 7th bit of the next data select function clk polarity selection transfer data i/o can be chosen to occur synchronously with the rising or the falling edge of the transfer clock lsb first, msb first selection whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected continuous receive mode selection reception is enabled immediately by reading the u0rb register notes: 1. when an external clock is selected, the conditions must be met while if the u0c0 register0 ckpol bit = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the ckpol bit in the u0c0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. if an overrun error occurs, the value of u0rb register will be indeterminate. the ir bit of s0ric register does not change. interrupt request generation timing table 13.1 clock synchronous serial i/o mode specifications
r8c/11 group 13.1 clock synchronous serial i/o mode rev.1.20 jan 27, 2006 page 115 of 204 rej09b0062-0120 register bit function u0tb 0 to 7 set transmission data u0rb 0 to 7 reception data can be read oer overrun error flag u0brg 0 to 7 set a bit rate u0mr smd2 to smd0 set to 001 2 ckdir select the internal clock or external clock u0c0 clk1 to clk0 select the count source for the u0brg register txept transmit register empty flag nch select txd0 pin output mode ckpol select the transfer clock polarity uform select the lsb first or msb first u0c1 te set this bit to 1 to enable transmission/reception ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag ucon u0irs select the source of uart0 transmit interrupt u0rrm set this bit to 1 to use continuous receive mode txdisel set to 0 txdien set to 0 table 13. 2 registers to be used and settings in clock synchronous serial i/o mode notes: 1. not all register bits are described above. set those bits to 0 when writing to the registers in clock synchronous serial i/o mode. table 13.3 lists the functions of the i/o pins during clock synchronous serial i/o mode. note that for a period from when the uart0 operation mode is selected to when transfer starts, the txd0 pin outputs an h . (if the nch bit is set to 1 (n-channel open-drain output), this pin is in high-impedance state.) table 13.3 pin functions pin name function method of selection txd 0 (p1 4 ) serial data output serial data input transfer clock output transfer clock input (outputs dummy data when performing reception only) rxd 0 (p1 5 ) clk 0 (p1 6 ) u0mr register ckdir bit=0 u0mr register ckdir bit=1 pd1 register pd1_6 bit=0 pd1 register pd1_5 bit=0 (p1 5 can be used as an input port when performing transmission only)
r8c/11 group 13.1 clock synchronous serial i/o mode rev.1.20 jan 27, 2006 page 116 of 204 rej09b0062-0120 figure 13.6 transmit and receive operation example of transmit timing (when internal clock is selected) stopped pulsing because the te bit = 0 write data to u0tb register tc = t clk = 2(n + 1) / fi fi: frequency of u0brg count source (f 1sio , f 8sio , f 32sio ) n: value set to u0brg register 0 1 0 1 0 1 0 1 transferred from u0tb register to uart0 transmit register the above timing diagram applies to the case where the register bits are set as follows: u0mr register ckdir bit = 0 (internal clock) u0c0 register ckpol bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the tran sfer clock) u0irs bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): set to 0 when interrupt request is accepted, or set by a program transfer clock u0c1 register te bit u0c1 register ti bit clk 0 txd 0 u0c0 register txept bit s0tic register ir bit d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk write dummy data to u0tb register transferred from u0tb register to uart0 transmit register f ext : frequency of external clock u0c1 register te bit clk 0 rxd 0 u0c1 register ri bit 0 1 0 1 u0c1 register re bit 0 1 s0ric register ir bit 0 1 make sure the following conditions are met when input to the clk0 pin before receiving data is high: u0c1 register te bit = 1 (transmit enabled) u0c1 register re bit = 1 (receive enabled) write dummy data to the u0tb register receive data is taken in read out from u0rb register transferred from uart0 receive register to u0rb register set to 0 when interrupt request is accepted, or set by a program the above timing diagram applies to the case where the register bits are set as follows: u0mr register ckdir bit = 1 (external clock) u0c0 register ckpol bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) 1 / f ext d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 0 1 u0c1 register ti bit example of receive timing (when external clock is selected)
r8c/11 group 13.1 clock synchronous serial i/o mode rev.1.20 jan 27, 2006 page 117 of 204 rej09b0062-0120 13.1.1 polarity select function figure 13.7 shows the polarity of the transfer clock. use the ckpol bit in the u0c0 register to select the transfer clock polarity. ( 2 ) w h e n t h e u 0 c 0 r e g i s t e r c k p o l b i t = 1 ( t r a n s m i t d a t a o u t p u t a t t h e r i s i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e f a l l i n g e d g e o f t h e t r a n s f e r c l o c k ) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d 0 r x d 0 c l k 0 (2 ) ( 1 ) w h e n t h e u 0 c 0 r e g i s t e r c k p o l b i t = 0 ( t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k ) d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d 0 r x d 0 c l k 0 (1 ) notes: 1. when not transferring, the clk0 pin outputs a high signal. 2. when not transferring, the clk0 pin outputs a low signal. figure 13.7 transfer clock polarity 13.1.2 lsb first/msb first select function figure 13.8 shows the transfer format. use the uform bit in the u0c0 register to select the transfer format. figure 13.8 transfer format ( 1 ) w h e n u 0 c 0 r e g i s t e r u f o r m b i t = 0 ( l s b f i r s t ) d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d 0 r x d 0 c l k 0 ( 2 ) w h e n u 0 c 0 r e g i s t e r u f o r m b i t = 1 ( m s b f i r s t ) d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d 0 r x d 0 c l k 0 n o t e s : 1 .t h i s a p p l i e s t o t h e c a s e w h e r e t h e c k p o l b i t i n t h e u 0 c 0 r e g i s t e r i s s e t t o 0 ( t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k ) .
r8c/11 group 13.1 clock synchronous serial i/o mode rev.1.20 jan 27, 2006 page 118 of 204 rej09b0062-0120 13.1.3 continuous receive mode continuous receive mode is held by setting setting the u0rrm bit in the ucon register to 1 (en- ables continuous receive mode). in this mode, reading the u0rb register sets the ti bit in the u0c1 register to 0 (data in the u0tb register). when the u0rrm bit is set to 1 , do not write dummy data to tge u0tb register in a program.
r8c/11 group 13.2 clock asynchronous serial i/o (uart) mode rev.1.20 jan 27, 2006 page 119 of 204 rej09b0062-0120 item specification transfer data format character bit (transfer data): selectable from 7, 8 or 9 bits start bit: 1 bit parity bit: selectable from odd, even, or none stop bit: selectable from 1 or 2 bits transfer clock uimr(i=0, 1) register ckdir bit = 0 (internal clock) : fj/(16(n+1)) fj=f 1sio , f 8sio , f 32sio n=setting value in uibrg register: 00 16 to ff 16 ckdir bit = 1 (external clock) : f ext /(16(n+1)) f ext : input from clki pin n=setting value in uibrg register: 00 16 to ff 16 transmission start condition before transmission can start, the following requirements must be met _ te bit in uic1 register= 1 (transmission enabled) _ ti bit in uic1 register = 0 (data present in uitb register) reception start condition before reception can start, the following requirements must be met _ re bit in uic1 register= 1 (reception enabled) _ start bit detection interrupt request for transmission, one of the following conditions can be selected generation timing _ uiirs bit = 0 (transmit buffer empty): when transferring data from uitb register to uarti transmit register (at start of transmission) _ uiirs bit =1 (transfer completed): when serial interface finished sending data from uarti transmit register for reception when transferring data from uarti receive register to uirb register (at completion of reception) error detection overrun error (1) this error occurs if serial interface started receiving the next data before reading uirb register and received the bit one before the last stop bit of the next data framing error this error occurs when the number of stop bits set is not detected parity error this error occurs when if parity is enabled, the number of 1 s in parity and character bits does not match the number of 1 s set error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function t x d 10 , r x d 1 selection (uart) p3 7 pin can be used as rxd 1 pin or txd 10 pin in uart1. select by a program. txd 11 pin selection (uart1) p0 0 pin can be used as txd 11 pin in uart1 or port p0 0 . select by a program. notes: 1. if an overrun error occurs, the value of u0rb register will be indeterminate. the ir bit in the s0ric register does not change. 13.2 clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. tables 13.4 lists the specifications of the uart mode. table 13.5 lists the registers and settings for uart mode. table 13.4 uart mode specifications
r8c/11 group 13.2 clock asynchronous serial i/o (uart) mode rev.1.20 jan 27, 2006 page 120 of 204 rej09b0062-0120 table 13.5 registers to be used and settings in uart mode register bit function uitb 0 to 8 set transmission data (1) uirb 0 to 8 reception data can be read (1) oer,fer,per,sum error flag uibrg 0 to 7 set a bit rate uimr smd2 to smd0 set these bits to 100 2 when transfer data is 7 bits long set these bits to 101 2 when transfer data is 8 bits long set these bits to 110 2 when transfer data is 9 bits long ckdir select the internal clock or external clock (2) stps select the stop bit pry, prye select whether parity is included and whether odd or even uic0 clk0, clk1 select the count source for the uibrg register txept transmit register empty flag nch select txdi pin output mode ckpol set to 0 uform lsb first or msb first can be selected when transfer data is 8 bits long. set this bit to 0 when transfer data is 7 or 9 bits long. uic1 te set this bit to 1 to enable transmission ti transmit buffer empty flag re set this bit to 1 to enable reception ri reception complete flag ucon u0irs, u1irs select the source of uart0/uart1 transmit interrupt u0rrm set to 0 txd1sel select output pin for uart1 transfer data txd1en select txd 10 or rxd 1 to be used notes: 1. the bits used for transmit/receive data are as follows: bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. an external clock can be selected in uart0 only. table 13.6 lists the functions of the i/o pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs an h . (if the nch bit is set to 1 (n-channel open-drain output), this pin is in high-impedance state.) table 13.6 i/o pin functions p i n n a m ef u n c t i o nm e t h o d o f s e l e c t i o n t x d 0 ( p 1 4 ) s e r i a l d a t a o u t p u t s e r i a l d a t a i n p u t p r o g r a m m a b l e i / o p o r t t r a n s f e r c l o c k i n p u t s e r i a l d a t a o u t p u t (cannot be used as a port when performing reception only) r x d 0 ( p 1 5 ) c l k 0 ( p 1 6 ) u0mr register ckdir bit=0 u0mr register ckdir bit=1 pd1 register pd1_6 bit=0 pd1 register pd1_5 bit=0 (can be used as an input port when performing transmission only) txd1en=1 txd1en=0, pd3 register pd3_7 bit=0 serial data output, txd1sel=1 s e r i a l d a t a o u t p u t s e r i a l d a t a i n p u t t x d 1 0 / r x d 1 ( p 3 7 ) t x d 1 1 ( p 0 0 )
r8c/11 group 13.2 clock asynchronous serial i/o (uart) mode rev.1.20 jan 27, 2006 page 121 of 204 rej09b0062-0120 txdi transfer clock uic1 register te bit uic1 register ti bit uic0 register txept bit sitic register ir bit tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj: frequency of uibrg count source (f 1sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n: value set to uibrg i: 0, 1 1 0 1 0 1 0 1 0 the above timing diagram applies to the case where the register bits are set as follows: uimr register prye bit = 1 (parity enabled) uimr register stps bit = 0 (1 stop bit) uiirs bit = 1 (an interrupt request occurs when transmit completed): set to 0 when interrupt request is accepted, or set by a program d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st psp d 0 d 1 st tc sp start bit parity bit stop bit stopped pulsing because the te bit = 0 write data to uitb register transferred from uitb register to uarti transmit register example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 13.9 transmit operation txdi transfer clock uic1 register te bit uic1 register ti bit uic0 register txept bit siric register ir bit 0 1 0 1 0 1 0 1 the above timing diagram applies to the case where the register bits are set as follows: uimr register prye bit = 0 (parity disabled) uimr register stps bit = 1 (2 stop bits) uiirs bit = 0 (an interrupt request occurs when transmit buffer becomes empty) tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp sp sp write data to uitb register transferred from uitb register to uarti transmit register set to 0 when interrupt request is accepted, or set by a program stop bit stop bit start bit tc = 16 (n + 1) / fj or 16 (n + 1) / f ext fj: frequency of uibrg count source (f 1sio , f 8sio , f 32sio ) f ext : frequency of uibrg count source (external clock) n: value set to uibrg i: 0, 1
r8c/11 group 13.2 clock asynchronous serial i/o (uart) mode rev.1.20 jan 27, 2006 page 122 of 204 rej09b0062-0120 example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 13.10 receive operation uibrg output rxdi transfer clock 1 0 0 1 0 1 uic1 register re bit uic1 register ri bit siric register ir bit start bit sampled l stop bit (ga 13 um60) set to 0 when interrupt request is accepted, or set by a program the above timing diagram applies to the case where the register bits are set as follows: uimr register prye bit = 0 (parity disabled) uimr register stps bit = 0 (1 stop bit) i = 0, 1 d 0 d 1 d 7 receive data taken in reception triggered when transfer clock is generated by falling edge of start bit transferred from uarti receive register to uirb register 13.2.1 txd 10 /rxd 1 select function (uart1) p3 7 can be used as txd 10 output pin or rxd 1 input pin by selecting with the txd1en bit in the ucon register. p3 7 is used as txd 10 output pin if the txd1en bit is set to 1 (txd 10 ) and used as rxd 1 input pin if set to 0 (rxd 1 ). 13.2.2 txd 11 select function (uart1) p0 0 can be used as txd 11 output pin or a port by selecting with the txd1sel bit in the ucon register. p0 0 is used as txd 11 output pin if the txd1sel bit is set to 1 (txd 11 ) and used as an i/o port if set to 0 (p0 0 ).
r8c/11 group 13.2 clock asynchronous serial i/o (uart) mode rev.1.20 jan 27, 2006 page 123 of 204 rej09b0062-0120 13.2.3 bit rate divided-by-16 of frequency by the uibrg (i=0 to 1) register in uart mode is a bit rate. when selecting internal clock setting value to the uibrg register = 1 fj : count source frequency of the uibrg register (f1sio, f8sio and f32sio) when selecting external clock setting value to the uibrg register = 1 fext : count source frequency of the uibrg register (external clock) fj bit rate ? ? figure 13.11 calculation formula of uibrg (i=0 to 1) register setting value table 13.7 bit rate setting example in uart mode bit rate brg system clock = 20mhz system clock = 8mhz (bps) count source brg setting value actual time(bps) error(%) brg setting value actual time(bps) error(%) 1200 f8 129 (81 16 ) 1201.92 0.16 51 (33 16 ) 1201.92 0.16 2400 f8 64 (40 16 ) 2403.85 0.16 25 (19 16 ) 2403.85 0.16 4800 f8 32 (20 16 ) 4734.85 1.36 12 (0c 16 ) 4807.69 0.16 9600 f1 129 (81 16 ) 9615.38 0.16 51 (33 16 ) 9615.38 0.16 14400 f1 86 (56 16 ) 14367.82 0.22 34 (22 16 ) 14285.71 0.79 19200 f1 64 (40 16 ) 19230.77 0.16 25 (19 16 ) 19230.77 0.16 28800 f1 42 (2a 16 ) 29069.77 0.94 16 (10 16 ) 29411.76 2.12 31250 f1 39 (27 16 ) 31250.00 0.00 15 (0f 16 ) 31250.00 0.00 38400 f1 32 (20 16 ) 37878.79 1.36 12 (0c 16 ) 38461.54 0.16 51200 f1 23 (17 16 ) 52083.33 1.73 9 (09 16 ) 50000.00 2.34
r8c/11 group rev.1.20 jan 27, 2006 page 124 of 204 rej09b0062-0120 14. a/d converter the a/d converter consists of one 10-bit successive approximation a/d converter circuit with a capacitive coupling amplifier. the analog inputs share the pins with p0 0 to p0 7 and p1 0 to p1 3 . therefore, when using these pins, make sure the corresponding port direction bits are set to 0 (input mode). when not using the a/d converter, set the vcut bit to 0 (vref unconnected), so that no current will flow from the v ref pin into the resistor ladder, helping to reduce the power consumption of the chip. the result of a/d conversion is stored in the ad register. table 14.1 shows the performance of the a/d converter. figure 14.1 shows a block diagram of the a/d converter, and figures 14.2 and 14.3 show the a/d converter-related registers. table 14.1 performance of a/d converter item performance method of a/d conversion successive approximation (capacitive coupling amplifier) analog input voltage (1) 0v to vref operating clock 8-bit resolution ? lsb 10-bit resolution ? lsb avcc = vref = 3.3 v 8-bit resolution ? lsb 10-bit resolution ? lsb operating modes one-shot mode and repeat mode (3) analog input pins 12 pins (an 0 to an 11 ) a/d conversion start condition adst bit in adcon0 register is set to 1 (a/d conversion starts) conversion speed per pin without sample and hold function 8-bit resolution: 49 with sample and hold function 8-bit resolution: 28
r8c/11 group rev.1.20 jan 27, 2006 page 125 of 204 rej09b0062-0120 1/2 figure 14.1 a/d converter block diagram 14. a/d converter
r8c/11 group rev.1.20 jan 27, 2006 page 126 of 204 rej09b0062-0120 a d c o n t r o l r e g i s t e r 0 ( 1 ) s y m b o la d d r e s sa f t e r r e s e t a d c o n 00 0 d 6 1 6 0 0 0 0 0 x x x 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a n a l o g i n p u t p i n s e l e c t b i t ( n o t e 4 ) c h 0 b i t s y m b o lb i t n a m e function c h 1 c h 2 a d o p e r a t i o n m o d e s e l e c t b i t (2 ) 0 : o n e - s h o t m o d e 1 : r e p e a t m o d e m d a d s t a / d c o n v e r s i o n s t a r t f l a g0 : a / d c o n v e r s i o n d i s a b l e d 1 : a / d c o n v e r s i o n s t a r t e d f r e q u e n c y s e l e c t b i t 0 (3 ) 0 : f a d / 4 i s s e l e c t e d 1 : f a d / 2 i s s e l e c t e d c k s 0 r w n o t e s : 1 . i f t h e a d c o n r e g i s t e r i s r e w r i t t e n d u r i n g a / d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . 2 . w h e n c h a n g i n g a / d o p e r a t i o n m o d e , s e t a n a l o g i n p u t p i n a g a i n . 3 . t h i s b i t i s v a l i d w h e n t h e c k s 1 b i t i n t h e a d c o n 1 r e g i s t e r i s s e t t o 0 . 4 . t h e a n a l o g i n p u t p i n c a n b e s e l e c t e d b y a c o m b i n a t i o n o f t h e c h 2 t o c h 0 b i t s a n d a d g s e l 0 b i t a s f o l l o w s : 0 0: port p0 group selected (an 0 to an 7 ) 1: port p1 group selected (an 8 to an 11 ) a d i n p u t g r o u p s e l e c t b i t (4 ) r w r w r w r w r w r w r w r w a d g s e l 0 set to 0 r e s e r v e d b i t ( b 5 ) a d c o n t r o l r e g i s t e r 1 ( 1 ) s y m b o l a d d r e s sa f t e r r e s e t a d c o n 10 0 d 7 1 6 0 0 1 6 b i t n a m e function bit symbol b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 n o t e s : 1 . i f t h e a d c o n 1 r e g i s t e r i s r e w r i t t e n d u r i n g a / d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . 2 . i n r e p e a t m o d e , t h e b i t s b i t m u s t b e s e t t o 0 ( 8 - b i t m o d e ) . 3 . t h e 0 ( v r e f u n c o n n e c t e d ) t o 1 ( v r e f c o n n e c t e d ) , w a i t f o r 1 s o r m o r e b e f o r e s t a r t i n g a / d c o n v e r s i o n . b i t s 8 / 1 0 - b i t m o d e s e l e c t b i t (2 ) 0 : 8-bit mode 1 : 10-bit mode v c u t v r e f c o n n e c t b i t (4 ) 0 : vref not connected 1 : vref connected f r e q u e n c y s e l e c t b i t 1 (3 ) c k s 1 0 0 0 0 0 set to 0 r e s e r v e d b i t ( b 2 - b 0 ) r w r w r w r w r w r w set to 0 r e s e r v e d b i t ( b 6 - b 7 ) 0 : cks0 bit in adcon0 register is valid 1 : f ad is selected c h 2 t o c h 0a d g s e l 0 = 0a d g s e l 0 = 1 0 0 0 2 0 0 1 2 0 1 0 2 0 1 1 2 1 0 0 2 1 0 1 2 1 1 0 2 1 1 1 2 a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 an 8 an 9 an 10 an 11 a v o i d t h e s e s e t t i n g s figure 14.2 adcon0 register and adcon1 register 14. a/d converter
r8c/11 group rev.1.20 jan 27, 2006 page 127 of 204 rej09b0062-0120 a d c o n t r o l r e g i s t e r 2 (1 ) s y m b o la d d r e s sa f t e r r e s e t a d c o n 20 0 d 4 1 6 0 0 1 6 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ad conversion method select bit 0 : w i t h o u t s a m p l e a n d h o l d 1 : w i t h s a m p l e a n d h o l d bit symbol bit name function r w n o t e s : 1 . i f t h e a d c o n 2 r e g i s t e r i s r e w r i t t e n d u r i n g a / d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . n o t h i n g i s a s s i g n e d . w h e n w r i t e , w r i t e 0 . w h e n r e a d , i t s c o n t e n t i s 0 . ad register s y m b o la d d r e s sa f t e r r e s e t a d 0 0 c 1 1 6 - 0 0 c 0 1 6 i n d e t e r m i n a t e w h e n b i t s b i t i n a d c o n 1 r e g i s t e r i s s e t t o 1 ( 1 0 - b i t m o d e ) f u n c t i o n ( b 1 5 ) b 7 b 7 b 0 b 0 (b 8 ) a/d conversion result nothing is assigned. when write, set to 0 . when read, its content is 0 . when read, its content is indeterminate. s m p 000 r e s e r v e d b i ts e t t o 0 ( b 3 - b 1 ) ( b 7 - b 4 ) r w r w r w ro r o 8 l o w - o r d e r b i t s o f a / d c o n v e r s i o n r e s u l t 2 high-order bits of a/d conversion result when bits bit in adcon1 register is set to 0 (8-bit mode) figure 14.3 adcon2 register and ad register 14. a/d converter
r8c/11 group rev.1.20 jan 27, 2006 page 128 of 204 rej09b0062-0120 item specification function input voltage on one pin selected by ch2 to ch0 and adgsel0 bit is a/d converted once. start condition set adst bit to 1 stop condition completion of a/d conversion (adst bit is set to 0 ) set adst bit to 0 interrupt request generation timing end of a/d conversion input pin one of an 0 to an 11 , as selected reading of result of a/d converter read ad register table 14.2 one-shot mode specifications 14.1 one-shot mode in one-shot mode, the input voltage on one selected pin is a/d converted once. table 14.2 lists the specifications of one-shot mode. figure 14.4 shows the adcon0 and adcon1 registers in one- shot mode. 14. one-shot mode
r8c/11 group rev.1.20 jan 27, 2006 page 129 of 204 rej09b0062-0120 a d c o n t r o l r e g i s t e r 0 (1 ) s y m b o la d d r e s sa f t e r r e s e t a d c o n 00 0 d 6 1 6 0 0 0 0 0 x x x 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 analog input pin select bit (2) (n ote 4 ) c h 0 b i t s y m b o lb i t n a m ef u n c t i o n ch1 c h 2 a d o p e r a t i o n m o d e s e l e c t b i t (2 ) 0 : one-shot mode m d adst a / d c o n v e r s i o n s t a r t f l a g 0 : a/d conversion disabled 1 : a/d conversion started f r e q u e n c y s e l e c t b i t 0 (3 ) 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 r w n o t e s : 1 . i f t h e a d c o n 0 r e g i s t e r i s r e w r i t t e n d u r i n g a / d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . 2 . w h e n c h a n g i n g a / d o p e r a t i o n m o d e , s e t a n a l o g i n p u t p i n a g a i n . 3 . t h i s b i t i s v a l i d w h e n t h e c k s 1 b i t i n t h e a d c o n 1 r e g i s t e r i s s e t t o 0 . 4 . t h e a n a l o g i n p u t p i n c a n b e s e l e c t e d b y a c o m b i n a t i o n o f t h e c h 2 t o c h 0 b i t s a n d a d g s e l 0 b i t a s f o l l o w s : 0 rw rw rw rw rw rw rw rw set to 0 reserved bit (b5) 0 a d c o n t r o l r e g i s t e r 1 (1 ) s y m b o l a d d r e s sa f t e r r e s e t a d c o n 10 0 d 7 1 6 0 0 1 6 bit name f u n c t i o n b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result is indeterminate. 2. the 0 (vref unconnected) to 1 (vref connected), wait for 1 ? or more before starting a/d conversion. b i t s 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut v r e f c o n n e c t b i t (3 ) 1 : v r e f c o n n e c t e d f r e q u e n c y s e l e c t b i t 1 (2 ) cks1 0 0 0 0 0 s e t t o 0 r e s e r v e d b i t (b2-b0) r w r w r w rw r w r w set to 0 reserved bit (b6-b7) 1 0 : cks0 bit in adcon0 register is valid 1 : f ad is selected ch2 to ch0 adgsel0=0 adgsel0=1 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 a n 8 a n 9 a n 1 0 a n 1 1 avoid these settings 0 : p o r t p 0 g r o u p s e l e c t e d ( a n 0 t o a n 7 ) 1 : p o r t p 1 g r o u p s e l e c t e d ( a n 8 t o a n 1 1 ) a d i n p u t g r o u p s e l e c t b i t (4 ) a d g s e l 0 figure 14.4 adcon0 register and adcon1 registers in one-shot mode 14. one-shot mode
r8c/11 group rev.1.20 jan 27, 2006 page 130 of 204 rej09b0062-0120 14.2 repeat mode in repeat mode, the input voltage on one selected pin is a/d converted repeatedly. table 14.3 lists the specifications of repeat mode. figure 14.5 shows the adcon0 and adcon1 registers in repeat mode. item specification function input voltage on one pin selected by ch2 to ch0 and adgsel0 bits is a/d converted repeatedly start condition set adst bit to 1 stop condition set adst bit to 0 interrupt request generation timing none generated input pin one of an 0 to an 11 , as selected reading of result of a/d converter read ad register table 14.3 repeat mode specifications 14. repeat mode
r8c/11 group rev.1.20 jan 27, 2006 page 131 of 204 rej09b0062-0120 a d c o n t r o l r e g i s t e r 0 (1 ) s y m b o la d d r e s sa f t e r r e s e t a d c o n 00 0 d 6 1 6 0 0 0 0 0 x x x 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 analog input pin select bit (2) c h 0 b i t s y m b o lb i t n a m ef u n c t i o n ch1 c h 2 ad operation mode select bit (2) 1 : r e p e a t m o d e md adst a / d c o n v e r s i o n s t a r t f l a g 0 : a/d conversion disabled 1 : a/d conversion started frequency select bit 0 (3) 0 : f a d / 4 i s s e l e c t e d 1 : f a d / 2 i s s e l e c t e d cks0 rw n o t e s : 1 . i f t h e a d c o n 0 r e g i s t e r i s r e w r i t t e n d u r i n g a / d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . 2 . w h e n c h a n g i n g a / d o p e r a t i o n m o d e , s e t a n a l o g i n p u t p i n a g a i n . 3 . t h i s b i t i s v a l i d w h e n t h e c k s 1 b i t i n t h e a d c o n 1 r e g i s t e r i s s e t t o 0 . 4 . t h e a n a l o g i n p u t p i n c a n b e s e l e c t e d b y a c o m b i n a t i o n o f t h e c h 2 t o c h 0 b i t s a n d a d g s e l 0 b i t a s f o l l o w s : 0 r w r w r w r w r w r w r w r w s e t t o 0 reserved bit ( b 5 ) 1 a d c o n t r o l r e g i s t e r 1 (1 ) s y m b o l a d d r e s sa f t e r r e s e t a d c o n 10 0 d 7 1 6 0 0 1 6 b i t n a m e function b i t s y m b o l b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 notes: 1. if the adcon1 register is rewritten during a/d conversion, the conversion result is indeterminate. 2. in repeat mode, the bits bit must be set to 0 (8-bit mode). 3. the f ad frequency must be 10 mhz or less. 4. if the vcut bit is reset from 0 (vref unconnected) to 1 (vref connected), wait for 1 ? or more before starting a/d conversion. bits 8/10-bit mode select bit (2) 0 : 8-bit mode vcut vref connect bit (4) 1 : v r e f c o n n e c t e d frequency select bit 1 (3) 0 : cks0 bit in adcon0 register is valid 1 : f ad is selected cks1 0 0 0 0 0 set to 0 reserved bit ( b 2 - b 0 ) rw rw rw rw rw rw set to 0 r e s e r v e d b i t ( b 6 - b 7 ) 1 0 (n ote 4 ) 0 : p o r t p 0 g r o u p s e l e c t e d ( a n 0 t o a n 7 ) 1 : p o r t p 1 g r o u p s e l e c t e d ( a n 8 t o a n 1 1 ) a d i n p u t g r o u p s e l e c t b i t (4 ) adgsel0 ch2 to ch0 adgsel0=0 adgsel0=1 000 2 001 2 010 2 011 2 100 2 101 2 110 2 111 2 a n 0 a n 1 a n 2 a n 3 a n 4 a n 5 a n 6 a n 7 a n 8 a n 9 a n 1 0 a n 1 1 avoid these settings figure 14.5 adcon0 register and adcon1 register in repeat mode 14. repeat mode
r8c/11 group rev.1.20 jan 27, 2006 page 132 of 204 rej09b0062-0120 14.3 sample and hold if the smp bit in the adcon2 register is set to ??(with sample-and-hold), the conversion speed per pin is increased to 28 ad cycles for 8-bit resolution or 33 ad cycles for 10-bit resolution. sample- and-hold is effective in all operation modes. select whether or not to use the sample-and-hold function before starting a/d conversion. when performing the a/d conversion, charge the comparator capacitor inside the microcomputer. figure 14.6 shows the a/d conversion timing diagram. 14.3 sample and hold/14.4 a/d conversion cycles sampling time 4 figure 14.6 a/d conversion timing diagram 14.4 a/d conversion cycles figure 14.7 shows the a/d conversion cycles. figure 14.7 a/d conversion cycles a/d conversion mode without sample & hold without sample & hold with sample & hold with sample & hold 8 bits 10 bits 8 bits 10 bits conversion time comparison time comparison time end process sampling time sampling time 49
r8c/11 group rev.1.20 jan 27, 2006 page 133 of 204 rej09b0062-0120 14.5 internal equivalent circuit of analog input 14.5 internal equivalent circuit of analog input figure 14.8 shows the internal equivalent circuit of analog input. figure 14.8 internal equivalent circuit to analog input v cc v cc v ss i =10 v ss sw2 sw1 an0 ani v ref parasitic diode parasitic diode on resistor approx. 2k ? ? ? ? ? ? ?
r8c/11 group rev.1.20 jan 27, 2006 page 134 of 204 rej09b0062-0120 14.6 inflow current bypass circuit 14.6 inflow current bypass circuit figure 14.9 shows the configuration of the inflow current bypass circuit, figure 14.10 shows the ex- ample of an inflow current bypass circuit where v cc or more is applied. figure 14.9 configuration of the inflow current bypass circuit to the internal logic of the a/d converter off on unselected channel fixed to gnd level off on off selected channel external input latched into on figure 14.10 example of an inflow current bypass circuit where v cc or more is applied to the internal logic of the a/d converter off on unselected channel leakage current generated unaffected by leakage leakage current generated off on off selected channel sensor input v cc or more on
r8c/11 group rev.1.20 jan 27, 2006 page 135 of 204 rej09b0062-0120 14.7 output impedance of sensor under a/d conversion to carry out a/d conversion properly, charging the internal capacitor c shown in figure 14.11 has to be completed within a specified period of time. t (sampling time) as the specified time. let output impedance of sensor equivalent circuit be r0, microcomputer s internal resistance be r, precision (error) of the a/d converter be x, and the a/d converter s resolution be y (y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). vc is generally vc = vin {1 e} and when t = t, vc=vin vin = vin(1 ) e= t = ln hence, r0 = r figure 14.11 shows analog input pin and external sensor equivalent circuit. when the difference between vin and vc becomes 0.1 lsb, we find impedance r0 when voltage between pins vc changes from 0 to vin (0.1/1024) vin in time t. (0.1/1024) means that a/d precision drop due to insufficient capacitor charge is held to 0.1 lsb at time of a/d conversion in the 10-bit mode. actual error however is the value of absolute precision added to 0.1 lsb. when f(x in ) = 10 mhz, t = 0.25 ? in the a/d conversion mode with sample & hold. output impedance r0 for sufficiently charging capaci- tor c within time t is determined as follows. t = 0.25 ? 2.8 x 10 3 7.3 x 10 3 thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the a/d converter turns out to be approximately 7.3 k ? ln t y x t c (r0 + r) 1 1 c (r0 + r) t 6.0 x 10 12 ln 1024 0.1 0.25 x 10 6 14.7 output impedance of sensor under a/d conversion
r8c/11 group rev.1.20 jan 27, 2006 page 136 of 204 rej09b0062-0120 figure 14.11 analog input pin and external sensor equivalent circuit r0 r ( 2 . 8 k ? ) c ( 6 p f ) vin v c n o t e : microcomputer s e n s o r e q u i v a l e n t c i r c u i t 1 . t h e c a p a c i t y o f t h e t e r m i n a l i s a s s u m e d t o b e 4 . 5 p f . 14.7 output impedance of sensor under a/d conversion
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 137 of 204 rej09b0062-0120 15. programmable i/o ports 15. 1 description the programmable input/output ports (hereafter referred to as i/o ports ) consist of 22 lines p0, p1, p3 0 to p3 3 , p3 7 , and p4 5 . each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4 lines. the port p1 allows the drive capacity of its n- channel output transistor to be set as necessary. the port p1 can be used as led drive port if the drive capacity is set to high . p4 6 and p4 7 can be used as an input only port if the main clock oscillation circuit is not used. figures 15.1 to 15.5 show the i/o ports. figure 15.6 shows the i/o pins. each pin functions as an i/o port or a peripheral function input/output. for details on how to set peripheral functions, refer to each functional description in this manual. if any pin is used as a peripheral function input, set the direction bit for that pin to 0 (input mode). any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set. 15.1.1 port pi direction register (pdi register, i = 0, 1, 3, 4) figure 15.7 shows the pdi register. this register selects whether the i/o port is to be used for input or output. the bits in this register correspond one for one to each port. 15.1.2 port pi register (pi register, i = 0 to 4) figure 15.8 shows the pi register. data i/o to and from external devices are accomplished by reading and writing to the pi register. the pi register consists of a port latch to hold the output data and a circuit to read the pin status. for ports set for input mode, the input level of the pin can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. for ports set for output mode, the port latch can be read by reading the corresponding pi register, and data can be written to the port latch by writing to the pi register. the data written to the port latch is output from the pin. the bits in the pi register correspond one for one to each port. 15.1.3 pull-up control register 0, pull-up control register 1 (pur0 and pur1 registers) figure 15.9 shows the pur0 and pur1 registers. the pur0 and pur1 register bits can be used to select whether or not to pull the corresponding port high in 4 bit units. the port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input mode. 15.1.4 port p1 drive capacity control register (drr register) figure 15.9 shows the drr register. the drr register is used to control the drive capacity of the port p1 n-channel output transistor. the bits in this register correspond one for one to each port.
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 138 of 204 rej09b0062-0120 figure 15.1 programmable i/o ports (1) p0 0 d a t a b u s pull-up selection analog input p0 1 to p0 7 d a t a b u s p u l l - u p s e l e c t i o n analog input d i r e c t i o n r e g i s t e r output " 1 " direction regiister p o r t l a t c h port latch p 1 0 t o p 1 2 data bus d i r e c t i o n r e g i s t e r p o r t l a t c h pull-up selection i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s select drive capacity analog input output "1" (n ote 1 ) n o t e s : 1 . s y m b o l i z e s a p a r a s i t i c d i o d e . m a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d v c c . ( n o t e 1 ) ( n o t e 1 )
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 139 of 204 rej09b0062-0120 p 1 4 data bus d i r e c t i o n r e g i s t e r port latch pull-up selection output "1" select drive capacity a n a l o g i n p u t p1 3 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p s e l e c t i o n s e l e c t d r i v e c a p a c i t y i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s p 1 5 data bus direction register p o r t l a t c h pull-up selection select drive capacity i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s ( n o t e 1 ) notes: 1. symbolizes a parasitic diode. make sure the input voltage on each pin will not exceed vcc. (n ote 1 ) ( n o t e 1 ) figure 15.2 programmable i/o ports (2)
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 140 of 204 rej09b0062-0120 figure 15.3 programmable i/o ports (3) p 3 0 , p 3 1 d a t a b u s p o r t l a t c h p u u - u p s e l e c t i o n o u t p u t " 1 " d i r e c t i o n r e g i s t e r p 1 6 , p 1 7 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p s e l e c t i o n o u t p u t " 1 " s e l e c t d r i v e c a p a c t i y i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s p 3 2 d a t a b u s p o r t l a t c h p u l l - u p s e l e c t i o n o u t p u t " 1 " d i r e c t i o n r e g i s t e r i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s ( n o t e 1 ) n o t e s : 1 . s y m b o l i z e s a p a r a s i t i c d i o d e . m a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d v c c . ( n o t e 1 ) ( n o t e 1 )
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 141 of 204 rej09b0062-0120 p 3 3 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p u l l - u p s e l e c t i o n i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s d i g i t a l f i l t e r p 3 7 d a t a b u s p o r t l a t c h p u l l - u p s e l e c t i o n o u t p u t " 1 " d i r e c t i o n r e g i s t e r i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s p 4 5 d a t a b u s p o r t l a t c h p u l l - u p s e l e c t i o n d i g i t a l f i l t e r i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s d i r e c t i o n r e g i s t e r ( n o t e 1 ) n o t e s : 1 . s y m b o l i z e s a p a r a s i t i c d i o d e . m a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d v c c . ( n o t e 1 ) ( n o t e 1 ) figure 15.4 programmable i/o ports (4)
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 142 of 204 rej09b0062-0120 figure 15.5 programmable i/o port (5) d a t a b u s data bus p 4 7 / x o u t p 4 6 / x i n (note 2) clocked inverter (1) n o t e s : 1 . w h e n c m 0 5 = 1 , c m 1 0 = 1 , o r c m 1 3 = 0 , t h e c l o c k e d i n v e r t e r i s c u t o f f . 2 . w h e n c m 1 0 = 1 o r c m 1 3 = 0 , t h e f e e d b a c k r e s i s t o r i s u n c o n n e c t e d . 3 . s y m b o l i z e s a p a r a s i t i c d i o d e . m a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d v c c . (note 3) figure 15.6 i/o pins m o d e m o d e s i g n a l i n p u t c n v s s c n v s s s i g n a l i n p u t r e s e t r e s e t s i g n a l i n p u t ( n o t e 1 ) ( n o t e 1 ) ( n o t e 1 ) n o t e s : 1 . s y m b o l i z e s a p a r a s i t i c d i o d e . m a k e s u r e t h e i n p u t v o l t a g e o n e a c h p i n w i l l n o t e x c e e d v c c .
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 143 of 204 rej09b0062-0120 p o r t p i r e g i s t e r ( i = 0 , 1 , 3 , 4 ) (1 , 2 ) s y m b o la d d r e s sa f t e r r e s e t p 00 0 e 0 1 6 i n d e t e r m i n a t e p 10 0 e 1 1 6 i n d e t e r m i n a t e p 30 0 e 5 1 6 i n d e t e r m i n a t e p 40 0 e 8 1 6 i n d e t e r m i n a t e b i t n a m ef u n c t i o n b i t s y m b o l r w b 7b 6b 5b 4b 3b 2b1b 0 p i _ 0p o r t p i 0 b i t p i _ 1p o r t p i 1 b i t p i _ 2p o r t p i 2 b i t p i _ 3p o r t p i 3 b i t p i _ 4p o r t p i 4 b i t p i _ 5p o r t p i 5 b i t p i _ 6p o r t p i 6 b i t p i _ 7p o r t p i 7 b i t the pin level on any i/o port which is set for input mode can be read by reading the corresponding bit in this register. the pin level on any i/o port which is set for output mode can be controlled by writing to the corresponding bit in this register 0 : l level 1 : h level ( i = 0 , 1 , 3 , 4 ) r w rw rw rw r w r w r w r w n o t e s : 1 . b i t s p 3 _ 4 t o p 3 _ 6 i n t h e p 3 r e g i s t e r a r e u n a v a i l a b l e o n t h i s m c u . i f i t i s n e c e s s a r y t o s e t b i t s p 3 _ 4 t o p 3 _ 6 , s e t t o 0 ( l l e v e l ) . w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e . 2 . b i t s p 4 _ 0 t o p 4 _ 4 i n t h e p 4 r e g i s t e r a r e u n a v a i l a b l e o n t h i s m c u . i f i t i s n e c e s s a r y t o s e t b i t s p 4 _ 0 t o p 4 _ 4 , s e t t o 0 ( l l e v e l ) . w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e . figure 15.8 p0 register to p4 register figure 15.7 pd0 register, pd1 register, pd3 register, and pd4 register p o r t p i d i r e c t i o n r e g i s t e r ( i = 0 , 1 , 3 , 4 ) (1 , 2 , 3 ) s y m b o la d d r e s sa f t e r r e s e t p d 00 0 e 2 1 6 0 0 1 6 p d 10 0 e 3 1 6 0 0 1 6 p d 30 0 e 7 1 6 0 0 1 6 p d 40 0 e a 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o lr w b 7b 6b 5b 4b 3b 2b 1b 0 p d i _ 0p o r t p i 0 d i r e c t i o n b i t p d i _ 1p o r t p i 1 d i r e c t i o n b i t p d i _ 2p o r t p i 2 d i r e c t i o n b i t p d i _ 3p o r t p i 3 d i r e c t i o n b i t p d i _ 4p o r t p i 4 d i r e c t i o n b i t p d i _ 5p o r t p i 5 d i r e c t i o n b i t p d i _ 6p o r t p i 6 d i r e c t i o n b i t p d i _ 7p o r t p i 7 d i r e c t i o n b i t 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) n o t e s : 1 . t h e p d 0 r e g i s t e r m u s t b e w r i t t e n t o b y t h e n e x t i n s t r u c t i o n a f t e r s e t t i n g t h e p r c 2 b i t i n t h e p r c r r e g i s t e r t o 1 ( w r i t e e n a b l e d ) . 2 . b i t s p d 3 _ 4 t o p d 3 _ 6 i n t h e p d 3 r e g i s t e r a r e u n a v a i l a b l e o n t h i s m c u . i f i t i s n e c e s s a r y t o s e t b i t s p d 3 _ 4 t o p d 3 _ 6 , s e t t o 0 ( i n p u t m o d e ) . w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e . 3 . b i t s p d 4 _ 0 t o p d 4 _ 4 , p d 4 _ 6 a n d p d 4 _ 7 i n t h e p d 4 r e g i s t e r a r e u n a v a i l a b l e o n t h i s m c u . i f i t i s n e c e s s a r y t o s e t b i t s p d 4 _ 0 t o p d 4 _ 4 , p d 4 _ 6 a n d p d 4 _ 7 , s e t t o 0 ( i n p u t m o d e ) . w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e . r w r w r w r w r w r w r w r w
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 144 of 204 rej09b0062-0120 p u l l - u p c o n t r o l r e g i s t e r 0 symbol address after reset pur0 00fc 16 00xx0000 2 b i t n a m ef u n c t i o n b i t s y m b o l r w b 7b 6b 5b4b 3b2b 1b 0 p u 0 0p 0 0 t o p 0 3 p u l l - u p (1 ) p u 0 1p 0 4 t o p 0 7 p u l l - u p ( 1 ) p u 0 2p 1 0 t o p 1 3 p u l l - u p ( 1 ) p u 0 6p 3 0 t o p 3 3 p u l l - u p ( 1 ) p u 0 7p 3 7 p u l l - u p ( 1 ) n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . w h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e . ( b 5 - b 4 ) 0 : n o t p u l l e d u p 1 : p u l l e d u p ( 1 ) pull-up control register 1 symbol address after reset pur1 00fd 16 xxxxxx0x 2 bit name function bit symbol b 7b 6b 5b4b 3b2b 1b 0 p u 1 1p 4 5 p u l l - u p ( 1 ) n o t e s : 1 . t h e p i n f o r w h i c h t h i s b i t i s 1 ( p u l l e d u p ) a n d t h e d i r e c t i o n b i t i s 0 ( i n p u t m o d e ) i s p u l l e d u p . r w r w r w p u 0 3p 1 4 t o p 1 7 p u l l - u p ( 1 ) r w r w r w rw rw p o r t p 1 d r i v e c a p a c i t y c o n t r o l r e g i s t e r symbol address after reset drr 00fe 16 00 16 bit name function bit symbol b 7b 6b5b 4b3b 2b 1b 0 drr0 p1 0 drive capacity d r r 1p 1 1 d r i v e c a p a c i t y d r r 2p 1 2 d r i v e c a p a c i t y d r r 3p 1 3 d r i v e c a p a c i t y d r r 4p 1 4 d r i v e c a p a c i t y d r r 5p 1 5 d r i v e c a p a c i t y 0 : low 1 : high r w r w r w r w rw rw r w 0 : not pulled up 1 : pulled up (1) 0 : not pulled up 1 : pulled up (1) nothing is assigned. when write, set to 0 . when read, its content is indeterminate. (b0) nothing is assigned. when write, set to 0 . when read, its content is indeterminate. ( b 7 - b 2 ) notes: 1. the p4 5 pin for which the pu11 bit is 1 (pulled up) and the pd4_5 bit is 0 (input mode) is pulled up. d r r 6p 1 6 d r i v e c a p a c i t y drr7 p1 7 drive capacit y r w r w set p1 n-channel output transistor drive capacity figure 15.9 pur0 register, pur1 register, and drr register
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 145 of 204 rej09b0062-0120 pd0 pd0_1 0 0 0 1 pur0 pu00 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 1100 2 xxxx table 15.1 port p0 0 /an 7 /t x d 11 setting 15.2 port setting table 15.1 to table 15.23 list the port setting. register bit setting value pd0 pd0_0 0 0 0 1 x x pur0 pu00 0 1 0 x x 0 adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 1110 2 xxxx xxxx xxxx ucon txd1sel x 0 x 0 x 0 x 0 1 1 u1mr smd2, smd0 00 2 xx 00 2 xx 00 2 xx 00 2 xx 1x x1 1x x1 u1c0 nch x x x x 0 1 function input port (not pulled up) input port (pulled up) a/d input (an 7 ) output port t x d 11 t x d 11 , n-channel open output table 15.2 port p0 1 /an 6 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 6 ) output port pd0 pd0_2 0 0 0 1 pur0 pu00 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 1010 2 xxxx table 15.3 port p0 2 /an 5 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 5 ) output port pd0 pd0_3 0 0 0 1 pur0 pu00 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 1000 2 xxxx table 15.4 port p0 3 /an 4 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 4 ) output port x: 0 or 1 x: 0 or 1 x: 0 or 1 x: 0 or 1
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 146 of 204 rej09b0062-0120 pd0 pd0_4 0 0 0 1 pur0 pu01 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 0110 2 xxxx table 15.5 port p0 4 /an 3 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 3 ) output port pd0 pd0_5 0 0 0 1 pur0 pu01 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 0100 2 xxxx table 15.6 port p0 5 /an 2 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 2 ) output port pd0 pd0_6 0 0 0 1 pur0 pu01 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 0010 2 xxxx table 15.7 port p0 6 /an 1 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 1 ) output port pd0 pd0_7 0 0 0 1 pur0 pu01 0 1 0 x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx 0000 2 xxxx table 15.8 port p0 7 /an 0 setting register bit setting value function input port (not pulled up) input port (pulled up) a/d input (an 0 ) output port _____ table 15.9 port p1 0 /ki 0 /an 8 /cmp0 0 setting register bit setting value pd1 pd1_0 0 0 0 0 1 1 x x pur0 pu02 0 1 0 0 x x x x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx xxxx 1001 2 xxxx xxxx xxxx xxxx tcout tcout0 0 0 0 0 0 0 1 1 function input port (not pulled up) input port (pulled up) _____ ki 0 input a/d input (an 8 ) output port output port (high drive) cmp0 0 output cmp0 0 output (high drive) drr drr0 x x x x 0 1 0 1 kien ki0en x x 1 x x x x x x: 0 or 1 x: 0 or 1 x: 0 or 1 x: 0 or 1 x: 0 or 1
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 147 of 204 rej09b0062-0120 _____ table 15.10 port p1 1 /ki 1 /an 9 /cmp0 1 setting register bit setting value pd1 pd1_1 0 0 0 0 1 1 x x pur0 pu02 0 1 0 0 x x x x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx xxxx 1011 2 xxxx xxxx xxxx xxxx tcout tcout1 0 0 0 0 0 0 1 1 function input port (not pulled up) input port (pulled up) _____ ki 1 input a/d input (an 9 ) output port output port (high drive) cmp0 1 output cmp0 1 output (high drive) drr drr1 x x x x 0 1 0 1 kien ki1en x x 1 x x x x x _____ table 15.11 port p1 2 /ki 2 /an 10 /cmp0 2 setting register bit setting value pd1 pd1_2 0 0 0 0 1 1 x x pur0 pu02 0 1 0 0 x x x x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx xxxx 1101 2 xxxx xxxx xxxx xxxx tcout tcout2 0 0 0 0 0 0 1 1 function input port (not pulled up) input port (pulled up) _____ ki 2 input a/d input (an 10 ) output port output port ( high drive) cmp0 2 output cmp0 2 output (high drive) drr drr2 x x x x 0 1 0 1 kien ki2en x x 1 x x x x x _____ table 15.12 port p1 3 /ki 3 /an 11 setting register bit setting value pd1 pd1_3 0 0 0 0 1 1 pur0 pu02 0 1 0 0 x x adcon0 ch2, ch1, ch0, adgsel0 xxxx xxxx xxxx 1111 2 xxxx xxxx function input port (not pulled up) input port (pulled up) _____ ki 3 input a/d input (an 11 ) output port output port (high drive) drr drr3 x x x x 0 1 kien ki3en x x 1 x x x x: 0 or 1 x: 0 or 1 x: 0 or 1
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 148 of 204 rej09b0062-0120 table 15.13 port p1 4 /t x d 0 setting register bit setting value pd1 pd1_4 0 0 1 1 x x x x pur0 pu03 0 1 x x x x x x u0mr smd2, smd0 00 2 00 2 00 2 00 2 x1 1x x1 1x x1 1x x1 1x function input port (not pulled up) input port (pulled up) output port output port ( high drive) t x d 0 output, cmos output t x d 0 output, cmos output (high drive) t x d 0 output, n-channel open output t x d 0 output, n-channel open output (high drive) drr drr4 x x 0 1 0 1 0 1 u0c0 nch x x x x 0 0 1 1 table 15.14 port p1 5 /r x d 0 setting register bit setting value pd1 pd1_5 0 0 0 1 1 pur0 pu03 0 1 0 x x function input port (not pulled up) input port (pulled up) r x d 0 input output port output port ( high drive) drr drr5 x x x 0 1 table 15.15 port p1 6 /clk 0 setting register bit setting value pd1 pd1_6 0 0 0 1 1 x x pur0 pu03 0 1 0 x x x x u0mr smd2, smd0, ckdir other than 010 2 other than 010 2 xx1 other than 010 2 other than 010 2 010 2 010 2 function input port (not pulled up) input port (pulled up) clk 0 (external clock) input output port output port ( high drive) clk 0 (internal clock) output clk 0 (internal clock) output ( high drive) drr drr6 x x x 0 1 0 1 x: 0 or 1 x: 0 or 1 x: 0 or 1
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 149 of 204 rej09b0062-0120 ____________ table 15.17 port p3 0 /cntr 0 /cmp1 0 setting register bit setting value pd3 pd3_0 0 0 1 x x pur0 pu06 0 1 x x x tcout tcout3 0 0 0 0 1 function input port (not pulled up) input port (pulled up) output port ____________ cntr 0 output cmp1 0 output txmr txocnt 0 0 0 1 x table 15.18 port p3 1 /tz out /cmp1 1 setting register bit setting value pd3 pd3_1 0 0 1 x x pur0 pu06 0 1 x x x tcout tcout4 0 0 0 0 1 function input port (not pulled up) input port (pulled up) output port tz out output cmp1 1 output tyzmr tzmod1, tzmod0 00 2 01 2 00 2 01 2 00 2 01 2 1x 01 2 xx tyzoc tzocnt x 1 x 1 x 1 x 0 x ________ table 15.19 port p3 2 /int 2 /cntr 1 /cmp1 2 setting register bit setting value pd3 pd3_2 0 0 0 1 x x pur0 pu06 0 1 0 x x x tcout tcout5 0 0 0 0 0 1 function input port (not pulled up) input port (pulled up) _______ cntr 1 /int 2 input output port cntr 1 output cmp1 2 output tyzmr tymod1 0 0 0 0 1 x tyzoc tzocnt 1 1 1 1 0 x _______ table 15.16 port p1 7 /int 1 /cntr 0 setting register bit setting value pd1 pd1_7 0 0 0 1 1 x x pur0 pu03 0 1 0 x x x x txmr txmod1, txmod0 other than 01 2 other than 01 2 other than 01 2 other than 01 2 other than 01 2 01 2 01 2 function input port (not pulled up) input port (pulled up) _______ cntr 0 /int 1 input output port output port ( high drive) cntr 0 output cntr 0 ( high drive) drr drr5 x x x 0 1 0 1 x: 0 or 1 x: 0 or 1 x: 0 or 1 x: 0 or 1
r8c/11 group 15. programmable i/o ports 15. programmable i/o ports rev.1.20 jan 27, 2006 page 150 of 204 rej09b0062-0120 table 15.21 port p3 7 /t x d 10 /r x d 1 setting register bit setting value pd3 pd3_7 0 0 0 1 x x pur0 pu07 0 1 0 x x x u1c0 nch x x x x 0 1 function input port (not pulled up) input port (pulled up) r x d 1 output port t x d 0 output, cmos output t x d 10 output, n-channel open output ucon txd1en x x 0 x 1 1 u1mr smd2, smd0 00 2 00 2 1x x1 00 2 1x x1 1x x1 _______ table 15.22 port p4 5 /int 0 setting register bit setting value pd4 pd4_5 0 0 0 1 pur1 pu11 0 1 0 x function input port (not pulled up) input port (pulled up) _______ int 0 input output port inten int0en 0 0 1 x table 15.23 port x in /p4 6 , x out /p4 7 setting register bit setting value cm1 cm13 1 1 1 1 0 cm1 cm10 1 0 0 0 x oscillation buffer off off off on off function x in -x out oscillatoin stop external input to x in pin, h output from x out pin x in -x out oscillatoin stop x in -x out oscillatoin input port cm0 cm05 1 1 1 0 x circuit specification feedback resistance off on on on off _______ table 15.20 port p3 3 /int 3 /tc in setting register bit setting value pd3 pd3_3 0 0 0 1 pur0 pu06 0 1 0 x function input port (not pulled up) input port (pulled up) tc in /int 3 input output port x: 0 or 1 x: 0 or 1 x: 0 or 1 x: 0 or 1
r8c/11 group 15. programmable i/o ports rev.1.20 jan 27, 2006 page 151 of 204 rej09b0062-0120 p i n n a m ec o n n e c t i o n p o r t s p 0 , p 1 , p 3 0 t o p 3 3 , p 3 7 p 4 5 a v c c , v r e f a v s s a f t e r s e t t i n g f o r i n p u t m o d e , c o n n e c t e v e r y p i n t o v s s v i a a r e s i s t o r ( p u l l - d o w n ) o r c o n n e c t e v e r y p i n t o v c c v i a a r e s i s t o r ( p u l l - u p ) s e t t o o u t p u t m o d e a n d l e a v e t h e s e p i n s o p e n (1 , 2 ) c o n n e c t t o v c c c o n n e c t t o v s s n o t e s : 1 . w h e n t h e s e p o r t s a r e s e t f o r o u t p u t m o d e a n d l e f t o p e n , t h e y r e m a i n i n p u t m o d e u n t i l t h e y a r e s e t f o r o u t p u t m o d e b y a p r o g r a m . t h e v o l t a g e l e v e l o f t h e s e p i n s m a y b e u n s t a b l e a n d t h e p o w e r s u p p l y c u r r e n t m a y i n c r e a s e f o r t h e t i m e t h e p o r t s r e m a i n i n p u t m o d e . t h e c o n t e n t o f t h e d i r e c t i o n r e g i s t e r s m a y c h a n g e d u e t o n o i s e o r r u n a w a y c a u s e d b y n o i s e . i n o r d e r t o e n h a n c e p r o g r a m r e l i a b i l i t y , s e t t h e d i r e c t i o n r e g i s t e r s p e r i o d i c a l l y b y a p r o g r a m . 2 . c o n n e c t t h e s e u n a s s i g n e d p i n s t o t h e m i c r o c o m p u t e r u s i n g t h e s h o r t e s t w i r e l e n g t h ( w i t h i n 2 c m ) p o s s i b l e . 3 . w h e n p o w e r - o n r e s e t i s u s e d . c o n n e c t t o v c c v i a r e s i s t o r ( p u l l - u p ) (2 ) p o r t s p 4 6 , p 4 7 c o n n e c t t o v c c v i a a r e s i s t o r ( p u l l - u p ) (2 ) r e s e t (3 ) table 15.24 unassigned pin handling 15.3 unassigned pin handling table 15.24 lists the handling of unassigned pins. figure 15.10 unassigned pin handling n o t e s : 1 . w h e n p o w e r - o n r e s e t f u n c t i o n i s u s e d . port p0, p1, p3 0 to p3 3 , p3 7 , p4 5 m i c r o c o m p u t e r (input mode) : : (input mode) (output mode) o p e n p o r t p 4 6 , p 4 7 r e s e t (1 ) a v c c / v r e f a v s s : :
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 152 of 204 rej09b0062-0120 16. electrical characteristics operating ambient temperature parameter unit supply voltage output voltage v o p d power dissipation storage temperature rated value v v condition v cc t stg t opr symbol mw v cc =av cc v av cc v -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 (d version) c topr=25 c analog supply voltage v cc =av cc -0.3 to 6.5 v i input voltage -0.3 to v cc +0.3 -0.3 to v cc +0.3 c table 16.1 absolute maximum ratings table 16.2 recommended operating conditions 2.7 5 . 5 t y p .m a x . unit p a r a m e t e r v c c s u p p l y v o l t a g e s y m b o l m i n . s t a n d a r d a n a l o g s u p p l y v o l t a g e v c c (3 ) a v c c v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h v s s a v s s 0.8v cc v v v cc 0.2v cc "l" input voltage " h " i n p u t v o l t a g e v f ( x i n ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y v v i l 10 3 . 0v < c / -40 to 85 c, unless otherwise specified. 2. the typical values when average output current is 100ms. 3. hold vcc=avcc. 0 i o h ( s u m ) " h " p e a k a l l o u t p u t c u r r e n t s conditions sum of all pins' ioh (peak) -60.0 m a i o h ( p e a k ) "h" peak output current -10.0 m a i o h ( a v g ) "h" average output current -5.0 ma i o l ( s u m ) "l" peak all output currents s u m o f a l l p i n s ' i o l ( p e a k ) 60 ma i ol (peak) " l " p e a k o u t p u t c u r r e n t except p1 0 to p1 7 p1 0 to p1 7 10 ma drive capacity high drive capacity low 3 0 10 m a ma i ol (avg) "l" average output current except p1 0 to p1 7 p1 0 to p1 7 d r i v e c a p a c i t y h i g h drive capacity low 5 1 5 5 ma ma ma 0 0 20
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 153 of 204 rej09b0062-0120 table 16.3 a/d conversion characteristics standard m i n .typ.m a x . r e s o l u t i o n bit v r e f = v c c 1 0 s y m b o lp a r a m e t e rm e a s u r i n g c o n d i t i o nunit lsb 3 r l a d d e r t c o n v l a d d e r r e s i s t a n c e c o n v e r s i o n t i m e r e f e r e n c e v o l t a g e analog input voltage v v i a v r e f 0v ref notes: 1. v cc =av cc =2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c, unless otherwise specified. 2. if f ad exceeds 10 mhz more, divide the f ad and hold a/d operating clock frequency ( ad) 10 mhz or below. 3. if the avcc is less than 4.2v, divide the f ad and hold a/d operating clock frequency ( ad) f ad /2 or below. 4. hold vcc=vref. ad=10 mhz, vref=vcc=5.0v v ref =v cc a b s o l u t e a c c u r a c y 1 0 b i t m o d e 8 bit mode a d = 1 0 m h z , v r e f = v c c = 5 . 0 v 2 l s b 1 0 b i t m o d e 8 b i t m o d e ad=10 mhz, vref=vcc=3.3v (3) 5l s b a d = 1 0 m h z , v r e f = v c c = 3 . 3 v (3 ) 2l s b 1 0 40 k ? a d = 1 0 m h z , v r e f = v c c = 5 . 0 v a d = 1 0 m h z , v r e f = v c c = 5 . 0 v 3 . 3 2 . 8 ? ? v a / d o p e r a t i n g c l o c k f r e q u e n c y ( 2 ) w i t h o u t s a m p l e & h o l d w i t h s a m p l e & h o l d 0.25 1 0 mhz 1.0 1 0 mhz v c c (4 ) p0 p1 p2 p3 p4 30pf figure 16.1 port p0 to p4 measurement circuit
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 154 of 204 rej09b0062-0120 b y t e p r o g r a m t i m e b l o c k e r a s e t i m e p r o g r a m , e r a s e v o l t a g e r e a d v o l t a g e 5 0 0 . 4 ? p a r a m e t e r standard m i n .t y p .m a x u n i t n o t e s : 1 . r e f e r e n c e d t o v c c 1 = a v c c = 2 . 7 t o 5 . 5 v a t t o p r = 0 t o 6 0 c u n l e s s o t h e r w i s e s p e c i f i e d . 2 . t h e d a t a h o l d t i m e i n c l u d e s t i m e t h a t t h e p o w e r s u p p l y i s o f f o r t h e c l o c k i s n o t s u p p l i e d . measuring condition s y m b o l p r o g r a m , e r a s e t e m p e r a t u r e 2.7 2.7 0 400 9 5 . 5 5 . 5 6 0 s v v c t i m e d e l a y f r o m s u s p e n d r e q u e s t u n t i l e r a s e s u s p e n d t d ( s r - e s ) p r o g r a m / e r a s e e n d u r a n c e 8 ms 100 t i m e s d a t a h o l d t i m e ( 2 ) a m b i e n t t e m p e r a t u r e = 5 5 c 20 y e a r e r a s e s u s p e n d r e q u e s t i n t e r v a l 10 m s table 16.4 flash memory version electrical characteristics table 16.5 voltage detection circuit electrical characteristics s y m b o l s t a n d a r d typ. unit measuring condition min. m a x . p a r a m e t e r v d e t v o l t a g e d e t e c t i o n l e v e l v 3 . 84 . 3 n o t e s : 1 . t h e m e a s u r i n g c o n d i t i o n i s v c c = a v c c = 2 . 7 v t o 5 . 5 v a n d t o p r = - 4 0 c t o 8 5 c . 2 . t h i s s h o w s t h e t i m e u n t i l t h e v o l t a g e d e t e c t i o n i n t e r r u p t r e q u e s t i s g e n e r a t e d s i n c e t h e v o l t a g e p a s s e s v d e t . 3 . t h i s s h o w s t h e r e q u i r e d t i m e u n t i l t h e v o l t a g e d e t e c t i o n c i r c u i t o p e r a t e s w h e n s e t t i n g t o " 1 " a g a i n a f t e r s e t t i n g t h e v c 2 7 b i t i n t h e v c r 2 r e g i s t e r t o 0 . v o l t a g e d e t e c t i o n i n t e r r u p t r e q u e s t g e n e r a t i n g t i m e (2 ) 4 0 na voltage detection circuit self consumption current waiting time till voltage detection circuit operation starts (3) td(e-a) v c 2 7 = 1 , v c c = 5 . 0 v 3 . 3 20 600 s s vccmin minimum value of microcomputer operation voltage 2.7 v fmr46 erase-suspend request (interrupt request) t d(sr-es) figure 16.2 time delay from suspend request until erase suspend
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 155 of 204 rej09b0062-0120 figure 16.3 reset circuit electrical characteristics v por1 v cc min v det (3) v det (3) t w(por1) t w(vpor1 vdet) sampling time (1, 2) internal reset signal ( l effective) f ring-s 1 x 32 f ring-s 1 x 32 v por2 notes: 1. hold the voltage of the microcomputer operation voltage range (vccmin or above) within sampling time. 2. a sampling clock is selectable. refer to 5.4 voltage detection circuit for details. 3. v det shows the voltage detection level of the voltage detection circuit. refer to 5.4 voltage detection circuit for details. 4. refer to table 16.6 reset circuit electrical characteristics for electrical characteristics. t w(por2) t w(vpor2 vdet) table 16.6 reset circuit electrical characteristics (when using hardware reset 2 (1, 3) ) symbol s t a n d a r d typ. unit measuring condition min. max. p a r a m e t e r v p o r 2 p o w e r - o n r e s e t v a l i d v o l t a g e v v d e t n o t e s : 1 . t h e v o l t a g e d e t e c t i o n c i r c u i t w h i c h i s e m b e d d e d i n a m i c r o c o m p u t e r i s a f a c t o r t o g e n e r a t e t h e h a r d w a r e r e s e t 2 . r e f e r t o 5 . 1 . 2 h a r d w a r e r e s e t 2 . 2 . t h i s c o n d i t i o n i s n o t a p p l i c a b l e w h e n u s i n g w i t h v c c 20 c c 20 c c, t w (por2) table 16.7 reset circuit electrical characteristics (when not using hardware reset 2) s y m b o l s t a n d a r d t y p . u n i t measuring condition m i n .m a x . p a r a m e t e r 0.1 n o t e s : 1 . w h e n n o t u s i n g h a r d w a r e r e s e t 2 , u s e w i t h v c c c c , t w ( p o r 1 ) 2 0 c c , t w ( p o r 1 ) c c , t w ( p o r 1 ) 2 0 c c 2 0 c c , t w ( p o r 1 )
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 156 of 204 rej09b0062-0120 table 16.10 electrical characteristics (1) [vcc=5v] s y m b o l v o h v o l " l " o u t p u t v o l t a g e "h" output voltage standard t y p . u n i t m e a s u r i n g c o n d i t i o n v v v min. max. v c c - 2 . 0 p a r a m e t e r i o h = - 5m a v h y s t e r e s i s " h " i n p u t c u r r e n t i i h " l " i n p u t c u r r e n t i i l v r a m r a m r e t e n t i o n v o l t a g e v t + - v t - 0.2 v ? at stop mode 2.0 v i =5v v i =0v r f x i n f e e d b a c k r e s i s t a n c e x i n m ? r p u l l u p p u l l - u p r e s i s t a n c e 1 6 7 k ? 3 0 12 5 n o t e s : 1 . r e f e r e n c e d t o v c c = a v c c = 4 . 2 t o 5 . 5 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( x i n ) = 2 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . v cc e x c e p t x o u t x out i oh = - 200? d r i v e a b i l i t y h i g h drive ability low v c c - 0 . 3 v cc v i oh = - 1 ma v cc - 2.0 v c c - 2 . 0 i o h = - 500 a v v v c c v cc except p1 0 to p1 7 , x out p1 0 to p1 7 x o u t drive capacity high drive capacity low i o l = 5 m a i o l = 2 0 0 a i ol = 15 ma i ol = 5 ma 2.0 0.45 v 2.0 2.0 v drive capacity high d r i v e c a p a c i t y l o w i ol = 1 ma i ol =500 ? 2.0 2.0 v reset 0.2 1.0 2.2 v 5. 0 - 5. 0 a v i = 0 v 50 1.0 f r i n g - s l o w - s p e e d o n - c h i p o s c i l l a t o r f r e q u e n c y 40 250 k h z drive capacity low i ol = 200 ? 0.45 v v i n t o , i n t 1 , i n t 2 , i n t 3 , k i 0 , k i 1 , k i 2 , k i 3 , c n t r 0 , c n t r 1 , t c i n , r x d 0 , r x d 1 , p 4 5 s y m b o l s t a n d a r d typ. unit m e a s u r i n g c o n d i t i o n m i n .m a x . p a r a m e t e r h i g h - s p e e d o n - c h i p o s c i l l a t o r f r e q u e n c y 1 / { t d ( h r o f f s e t ) + t d ( h r ) } w h e n t h e r e s e t i s r e l e a s e d n o t e s : 1 . t h e m e a s u r i n g c o n d i t i o n i s v c c = a v c c = 5 . 0 v a n d t o p r = 2 5 c . h i g h - s p e e d o n - c h i p o s c i l l a t o r p e r i o d a d j u s t e d u n i t mhz ns v c c = 5 . 0 v , t o p r = 2 5 c s e t " 0 0 1 6 " i n t h e h r 1 r e g i s t e r 8 61 d i f f e r e n c e s w h e n s e t t i n g " 0 1 1 6 " a n d " 0 0 1 6 " i n t h e h r r e g i s t e r s e t t a b l e h i g h - s p e e d o n - c h i p o s c i l l a t o r m i n i m u m p e r i o d h i g h - s p e e d o n - c h i p o s c i l l a t o r f r e q u e n c y t e m p e r a t u r e d e p e n d e n c e ( 1 ) t d ( h r o f f s e t ) t d ( h r ) v c c = 5 . 0 v , t o p r = 2 5 c s e t " 4 0 1 6 " i n t h e h r 1 r e g i s t e r 1 ns f r e q u e n c y f l u c t u a t i o n i n t e m p e r a t u r e r a n g e o f - 1 0 c t o 5 0 c ? % % h i g h - s p e e d o n - c h i p o s c i l l a t o r f r e q u e n c y t e m p e r a t u r e d e p e n d e n c e ( 2 ) frequency fluctuation in temperature range of -40 c to 85 c ?0 6 1 0 table 16.8 high-speed on-chip oscillator circuit electrical characteristics s y m b o l s t a n d a r d t y p . u n i t measuring condition m i n .m a x . p a r a m e t e r 2 0 0 0 n o t e s : 1 . t h e m e a s u r i n g c o n d i t i o n i s v c c = a v c c = 2 . 7 t o 5 . 5 v a n d t o p r = 2 5 c . 2 . t h i s s h o w s t h e w a i t t i m e u nt i l t h e i n t e r n a l p o w e r s u p p l y g e n e r a t i n g c i r c u i t i s s t a b i l i z e d d u r i n g p o w e r - o n . 3 . t h i s s h o w s t h e t i m e u n t i l c p u c l o c k s u p p l y s t a r t s f r o m t h e i n t e r r u p t a c k n o w l e d g e m e n t t o c a n c e l s t o p m o d e . 150 t d ( r - s ) stop release time (3) s t d ( p - r ) t i m e f o r i n t e r n a l p o w e r s u p p l y s t a b i l i z a t i o n d u r i n g p o w e r i n g - o n (2 ) ? 1 table 16.9 power circuit timing characteristics
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 157 of 204 rej09b0062-0120 s y m b o l s t a n d a r d typ. u n i t m e a s u r i n g c o n d i t i o n m i n .m a x . p a r a m e t e r n o di v i s i on m a i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s 91 5 x in =20 mh z ( square wave ) m a h i g h - s p e e d m o d e i c c p o w e r s u p p l y c u r r e n t ( v c c =3 . 3 t o 5 . 5 v ) 4 7 0 notes: 1. timer y is operated with timer mode. 2. referenced to v cc = av cc = 4.2 to 5.5v at topr = -20 to 85 c / -40 to 85 c, f(x in )=20mhz unless otherwise specified. m a medium-speed mode high-speed on-chip oscillator mode l o w - s p e e d o n - c h i p o s c i l l a t o r m o d e hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z x in =16 mh z ( square wave ) hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z n o di v i s i on 8 x i n = 2 0 m h z ( s q u a r e w a v e ) hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z di v i s i on b y 8 4 x i n = 1 6 m h z ( s q u a r e w a v e ) hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z di v i s i on b y 8 3 m a m a i n c l o c k o f f hi g h -spee d on-c hi p osc ill ator on=8 mh z l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z n o d i v i s i o n 4 8 m a m a i n c l oc k o ff l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z d i v i s i o n b y 8 ma 1.5 m a i n c l o c k o f f h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z h i g h - s p e e d o n - c h i p o s c i l l a t o r o n = 8 m h z m a x in =10 mh z ( square wave ) hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z n o di v i s i on 5 x i n = 1 0 m h z ( s q u a r e w a v e ) hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z di v i s i on b y 8 2 m a 14 9 0 0 wait mode a di v i s i on b y 8 m a i n c l o c k o f f hi g h -spee d on-c hi p osc ill ator o ff l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z w h e n a w a i t i n s t r u c t i o n i s e x e c u t e d ( 1 ) p e r i p h e r a l c l o c k o p e r a t i o n 40 ? wait mode m a i n c l oc k o ff h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l ow-spee d on-c hi p osc ill ator on=125 kh z when a wait instruction is executed (1) p er i p h era l c l oc k o ff 38 76 80 a stop mode m a i n c l o c k o f f , t o p r = 2 5 c hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator o ff c m 1 0 = " 1 " p er i p h era l c l oc k o ff 0 . 8 3 . 0 vc 27="0" vc 27= 0 vc 27= 0 ? table 16.11 electrical characteristics (2) [vcc=5v]
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 158 of 204 rej09b0062-0120 timing requirements (unless otherwise noted: v cc = 5v, v ss = 0v at topr = 25 c) [v cc =5v] table 16.12 x in input ________ table 16.13 cntr0 input, cntr1 input, int2 input ________ table 16.14 tcin input, int3 input table 16.15 serial interface ________ table 16.16 external interrupt int0 input symbol t c (x in ) t wh (x in ) t wl (x in ) parameter x in input cycle time x in input high pulse width x in input low pulse width min. 50 25 25 max. unit ns ns ns standard symbol t c ( cntr0 ) t wh ( cntr0 ) t wl ( cntr0 ) parameter cntr0 input cycle time cntr0 input high pulse width cntr0 input low pulse width min. 100 40 40 max. unit ns ns ns standard symbol t c ( tcin ) t wh ( tcin ) t wl ( tcin ) parameter tcin input cycle time tcin input high pulse width tcin input low pulse width min. 400 (1) 200 (2) 200 (2) max. unit ns ns ns standard notes: 1. when using the timer c input capture mode, adjust the cycle time above ( 1/ timer c count source frequency x 3). 2. when using the timer c input capture mode, adjust the pulse width above ( 1/ timer c count source frequency x 1.5). notes: ________ ________ 1. when selecting the digital filter by the int0 input filter select bit, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. ________ ________ 2. when selecting the digital filter by the int0 input filter select bit, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. symbol t c ( ck ) t w ( ckh ) t w ( ckl ) t d ( c-q ) t h ( c-q ) t su ( d-c ) t h ( c-d ) parameter clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time min. 200 100 100 0 35 90 max. unit ns ns ns ns ns ns ns standard 80 symbol t w ( inh ) t w ( inl ) parameter ________ int0 input high pulse width ________ int0 input low pulse width min. 250 (1) 250 (2) max. unit ns ns standard
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 159 of 204 rej09b0062-0120 figure 16.4 vcc=5v timing diagram clk i txd i rxd i int i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 5v
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 160 of 204 rej09b0062-0120 s y m b o l v oh v o l " l " o u t p u t v o l t a g e " h " o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v v v m i n .m a x . v c c - 0 . 5 p a r a m e t e r i oh = - 1ma v h y s t e r e s i s " h " i n p u t c u r r e n t i i h " l " i n p u t c u r r e n t i i l v r a m r a m r e t e n t i o n v o l t a g e v t + - v t - 0 . 2 v a at stop mode 2 . 0 v i = 3 v r f x i n f e e d b a c k r e s i s t a n c e x in m ? ? c / -40 to 85 c, f(x in )=10mhz unless otherwise specified. v c c e x c e p t x o u t x out drive capacity high drive capacity low i oh = - 0.1 ma v c c - 0 . 5 v c c - 0 . 5 i oh = - 50 a v v v c c v c c except p1 0 to p1 7 , x out p 1 0 t o p 1 7 x o u t d r i v e c a p a c i t y h i g h d r i v e c a p a c i t y l o w i ol = 1 ma i o l = 2 m a i o l = 1 m a 0 . 5 v 0.5 0.5 v drive capacity high drive capacity low i o l = 0 . 1 m a i o l = 5 0 a 0 . 5 0 . 5 v r e s e t 0 . 2 0 . 8 1 . 8 v 4.0 - 4. 0a v i =0v 160 3.0 f r i n g - s l o w - s p e e d o n - c h i p o s c i l l a t o r f r e q u e n c y 40 2 5 0 khz v i =0v 5 0 0 i n t o , i n t 1 , i n t 2 , i n t 3 , k i 0 , k i 1 , k i 2 , k i 3 , c n t r 0 , c n t r 1 , t c i n , r x d 0 , r x d 1 , p 4 5 table 16.17 electrical characteristics (3) [vcc=3v]
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 161 of 204 rej09b0062-0120 table 16.18 electrical characteristics (4) [vcc=3v] s y m b o l s t a n d a r d t y p . u n i t measuring condition min. m a x . p a r a m e t e r n o di v i s i on m a i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s 813 x in =20 mh z ( square wave ) m a high-speed mode i c c p o w e r s u p p l y c u r r e n t ( v c c =2 . 7 t o 3 . 3 v ) 4 2 0 n o t e s : 1 . t i m e r y i s o p e r a t e d w i t h t i m e r m o d e . 2. r e f e r e n c e d t o v c c = a v c c = 2 . 7 t o 3 . 3 v a t t o p r = - 2 0 t o 8 5 c / - 4 0 t o 8 5 c , f ( x i n ) = 1 0 m h z u n l e s s o t h e r w i s e s p e c i f i e d . w a i t m o d e a ? m a medium-speed mode high-speed on-chip oscillator mode low-speed on-chip oscillator mode h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z x in =16 mh z ( square wave ) h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z n o di v i s i on 7 x i n = 2 0 m h z ( s q u a r e w a v e ) h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z d i v i s i o n b y 8 3 x i n = 1 6 m h z ( s q u a r e w a v e ) h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z d i v i s i o n b y 8 2 . 5 m a m a i n c l o c k o f f h i g h - s p e e d o n - c h i p o s c i l l a t o r o n = 8 m h z l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z n o d i v i s i o n 3 . 5 7 . 5 m a m a i n c l oc k o ff l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z d i v i s i o n b y 8 m a 1 . 5 m a i n c l oc k o ff hi g h -spee d on-c hi p osc ill ator o ff l ow-spee d on-c hi p osc ill ator on=125 kh z di v i s i on b y 8 m a i n c l oc k o ff h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l ow-spee d on-c hi p osc ill ator on=125 kh z w h e n a w a i t i n s t r u c t i o n i s e x e c u t e d (1) p er i p h era l c l oc k operat i on 37 h i g h - s p e e d o n - c h i p o s c i l l a t o r o n = 8 m h z m a x in =10 mh z ( square wave ) h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z n o di v i s i on 5 x i n = 1 0 m h z ( s q u a r e w a v e ) h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z d i v i s i o n b y 8 1 . 6 m a 12 800 ? wait mode m a i n c l o c k o f f hi g h -spee d on-c hi p osc ill ator o ff l o w - s p e e d o n - c h i p o s c i l l a t o r o n = 1 2 5 k h z when a wait instruction is executed (1) p er i p h era l c l oc k o ff 35 70 74 s t o p m o d e m a i n c l oc k o ff , t opr = 25 c h i g h - s p e e d o n - c h i p o s c i l l a t o r o f f l ow-spee d on-c hi p osc ill ator o ff cm 10="1" p er i p h era l c l oc k o ff 0 . 7 3 . 0 vc 27="0" vc 27= 0 vc 27= 0 ?
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 162 of 204 rej09b0062-0120 timing requirements (unless otherwise noted: v cc = 3v, v ss = 0v at topr = 25 c) [v cc =3v] table 16.19 x in input ________ table 16.20 cntr0 input, cntr1 input, int2 input ________ table 16.21 tcin input, int3 input table 16.22 serial interface ________ table 16.23 external interrupt int0 input symbol t c (x in ) t wh (x in ) t wl (x in ) parameter x in input cycle time x in input high pulse width x in input low pulse width min. 100 40 40 max. unit ns ns ns standard symbol t c ( cntr0 ) t wh ( cntr0 ) t wl ( cntr0 ) parameter cntr0 input cycle time cntr0 input high pulse width cntr0 input low pulse width min. 300 120 120 max. unit ns ns ns standard symbol t c ( tcin ) t wh ( tcin ) t wl ( tcin ) parameter tcin input cycle time tcin input high pulse width tcin input low pulse width min. 1200 (1) 600 (2) 600 (2) max. unit ns ns ns standard notes: 1. when using the timer c input capture mode, adjust the cycle time above ( 1/ timer c count source frequency x 3). 2. when using the timer c input capture mode, adjust the pulse width above ( 1/ timer c count source frequency x 1.5). notes: ________ ________ 1. when selecting the digital filter by the int0 input filter select bit, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. ________ ________ 2. when selecting the digital filter by the int0 input filter select bit, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. symbol t c ( ck ) t w ( ckh ) t w ( ckl ) t d ( c-q ) t h ( c-q ) t su ( d-c ) t h ( c-d ) parameter clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time min. 300 150 150 0 55 90 max. unit ns ns ns ns ns ns ns standard 160 symbol t w ( inh ) t w ( inl ) parameter ________ int0 input high pulse width ________ int0 input low pulse width min. 380 (1) 380 (2) max. unit ns ns standard
r8c/11 group 16. electrical characteristics rev.1.20 jan 27, 2006 page 163 of 204 rej09b0062-0120 figure 16.5 vcc=3v timing diagram clk i txd i rxd i int i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 3v
r8c/11 group 17. flash memory version rev.1.20 jan 27, 2006 page 164 of 204 rej09b0062-0120 table 17.1 flash memory version performance 17. flash memory version 17.1 overview the flash memory version has two modes cpu rewrite and standard serial i/o in which its flash memory can be operated on. table 17.1 outlines the performance of flash memory version (see table 1.1 performance for the items not listed on table 17.1). item flash memory operating mode erase block method for program method for erasure program, erase control method protect method number of commands number of program and erasure rom code protection specification 2 modes (cpu rewrite and standard serial i/o) see figure 17.1. flash memory block diagram in units of byte block erase program and erase controlled by software command blocks 0 and 1 protected by block 0, 1 program enable bit 5 commands 100 times standard serial i/o mode is supported. table 17.2 flash memory rewrite modes flash memory cpu rewrite mode standard serial i/o mode rewrite mode function areas which user rom area user rom area can be rewritten operation single chip mode boot mode mode rom none serial programmer programmer user rom area is rewritten by executing software commands from the cpu. ew0 mode: can be rewritten in any area other than the flash memory ew1 mode: can be rewritten in the flash memory user rom area is rewritten by using a dedicated serial programmer. standard serial i/o mode 1 : clock synchronous serial i/o standard serial i/o mode 2 : uart
r8c/11 group 17. memory map rev.1.20 jan 27, 2006 page 165 of 204 rej09b0062-0120 17.2 memory map the rom in the flash memory version is separated between a user rom area and a boot rom area (reserved area). figure 17.1 shows the block diagram of flash memory. the user rom area is divided into several blocks. the user rom area can be rewritten in cpu rewrite and standard serial input/output modes. block 1 and block 0 are enabled for rewrite in cpu rewrite mode by setting the fmr02 bit in the fmr0 register to 1 (rewrite enabled). the rewrite program for standard serial i/o mode is stored in the boot rom area before shipment. the boot rom area and the user rom area share the same address, but have an another memory. figure 17.1 flash memory block diagram 8 k b y t e s 0 f f f f 1 6 boot rom area (reserved area) (2) notes: 1. when setting the fmr02 bit in the fmr0 register to 1 (rewrite enabled) and the fmr15 bit in the fmr1 register to 0 (rewrite enabled), the block 0 is rewritable. when setting the fmr16 bit to 0 (rewrite enabled), the block 1 is rewritable (only for cpu rewrite mode). 2. this area is to store the boot program provided by renesas technology. b l o c k 0 : 8 k b y t e s ( 1 ) b l o c k 1 : 8 k b y t e s (1 ) 0 f f f f 1 6 0 e 0 0 0 1 6 user rom area 0 c 0 0 0 1 6 0 d f f f 1 6 0 e 0 0 0 1 6 block 0 : 8 kbytes (1) block 1 : 4 kbytes (1) 0 f f f f 1 6 user rom area 0 d 0 0 0 1 6 0 d f f f 1 6 0 e 0 0 0 1 6 block 0 : 8 kbytes (1) 0 f f f f 1 6 user rom area 0 e 0 0 0 1 6 1 6 k b y t e s r o m p r o d u c t 12 kbytes rom product 8 kbytes rom product
r8c/11 group rev.1.20 jan 27, 2006 page 166 of 204 rej09b0062-0120 17.3 functions to prevent flash memory from rewriting to prevent the flash memory from being read or rewritten easily, standard serial i/o mode has an id code check function. 17.3.1 id code check function use this function in standard serial i/o mode. unless the flash memory is blank, the id codes sent from the programmer and the id codes written in the flash memory are compared to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, the areas of which, beginning with the first byte, are 00ffdf 16 , 00ffe3 16 , 00ffeb 16 , 00ffef 16 , 00fff3 16 , 00fff7 16 , and 00fffb 16 . prepare a program in which the id codes are preset at these addresses and write it in the flash memory. figure 17.2 address for id code stored reset vector o sc ill at i on stop d etect i on/ w atc hd og timer vector/ voltage detection single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 (reserved) ( r e s e r v e d ) 0 0 f f f f 1 6 t o 0 0 f f f c 1 6 00fffb 16 to 00fff8 16 0 0 f f f 7 1 6 t o 0 0 f f f 4 1 6 0 0 f f f 3 1 6 t o 0 0 f f f 0 1 6 00ffef 16 to 00ffec 16 0 0 f f e b 1 6 t o 0 0 f f e 8 1 6 00ffe7 16 to 00ffe4 16 0 0 f f e 3 1 6 t o 0 0 f f e 0 1 6 0 0 f f d f 1 6 t o 0 0 f f d c 1 6 4 bytes address (n ote 1 ) n o t e s : 1 . w h e n w r i t e t o a d d r e s s 0 0 f f f f 1 6 , w r i t e f f 1 6 . 17.3 functions to prevent flash memory from rewriting 17.3 functions to prevent flash memory from rewriting
r8c/11 group rev.1.20 jan 27, 2006 page 167 of 204 rej09b0062-0120 17.4 cpu rewrite mode in cpu rewrite mode, the user rom area can be rewritten by executing software commands from the cpu. therefore, the user rom area can be rewritten directly while the microcomputer is mounted on- board without having to use a rom programmer, etc. make sure the program and the block erase commands are executed only on each block in the user rom area. for interrupts requested during an erase operation in cpu rewrite mode, the r8c/11 flash module offers an "erase-suspend" feature which allow the erase operation to be suspended, and access made avail- able to the flash. during cpu rewrite mode, the user rom area be operated on in either erase write 0 (ew0) mode or erase write 1 (ew1) mode. table 17.3 lists the differences between erase write 0 (ew0) and erase write 1 (ew1) modes. table 17.3 ew0 mode and ew1 mode item ew0 mode ew1 mode operation mode single chip mode single chip mode areas in which a user rom area user rom area rewrite control program can be located areas in which a must be transferred to any area other can be executed directly in the user rewrite control than the flash memory (e.g., ram) rom area program can be executed before being executed areas which can be user rom area user rom area rewritten however, this does not include the block in which a rewrite control program exists (1) software command none program, block erase command limitations cannot be executed on any block in which a rewrite control program exists read status register command cannot be executed modes after program or read status register mode read array mode erase cpu status during auto operating hold state (i/o ports retain the state in write and auto erase which they were before the command was executed) flash memory status read the fmr0 register fmr00, read the fmr0 register fmr00, detection fmr06, and fmr07 bits in a fmr06, and fmr07 bits in a program program execute the read status register command to read the status register sr7, sr5, and sr4. conditions for set the fmr40 and fmr41 bits in when an interrupt which is set for transferring to the fmr4 register to 1 by program. enabled occurs while the fmr40 bit in erase-suspend the fmr4 register is set to 1 . notes: 1. block 1 and block 0 are enabled for rewrite by setting the fmr02 bit in the fmr0 register to 1 (rewrite enabled). 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 168 of 204 rej09b0062-0120 17.4.1 ew0 mode the microcomputer is placed in cpu rewrite mode by setting the fmr01 bit in the fmr0 register to 1 (cpu rewrite mode enabled), ready to accept commands. in this case, because the fmr1 register's fmr11 bit = 0, ew0 mode is selected. use software commands to control program and erase operations. read the fmr0 register or status register to check the status of program or erase operation at completion. when moving to an erase-suspend during auto-erase, set the fmr40 bit to 1 (erase-suspend en- abled ) and the fmr41 bit to 1 (erase-suspend requested). wait for td(sr-es) and make sure that the fmr46 bit is set to 1 (enables reading) before accessing the user rom space. the auto-erase operation resumes by setting the fmr41 bit to 0 (erase restart). 17.4.2 ew1 mode ew1 mode is selected by setting fmr11 bit to 1 (ew1 mode) after setting the fmr01 bit to 1 (cpu rewrite mode enabled). read the fmr0 register to check the status of program or erase operation at completion. avoid ex- ecuting software commands of read status register in ew1 mode. to enable the erase-suspend function, the block erase command should be executed after setting the fmr40 bit to 1 (erase-suspend enabled). an interrupt to request an erase-suspend must be in en- abled state. after passing td(sr-es) since the block erase command is executed, an interrupt request can be acknowledged. when an interrupt request is generated, fmr41 bit is automatically set to 1 (erase-suspend re- quested) and the auto-erase operation is halted. if the auto-erase operation is not completed (fmr00 bit is 0 ) when the interrupt routine is ended, the block erase command should be executed again by setting the fmr41 bit to 0 (erase restart). 17.4 cpu rewrite mode 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 169 of 204 rej09b0062-0120 figure 17.3 shows the fmr0 register. figure 17.4 shows the fmr1 and fmr4 registers. fmr00 bit this bit indicates the operating status of the flash memory. the bit is 0 during programming, eras- ing, or erase-suspend mode; otherwise, the bit is 1 . fmr01 bit the microcomputer is made ready to accept commands by setting the fmr01 bit to 1 (cpu rewrite mode). fmr02 bit the block1 and block0 do not accept the program and block erase commands if the fmr02 bit is set to 0 (rewrite disabled). fmstp bit this bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. the flash memory is disabled against access by setting the fmstp bit to 1 . therefore, the fmstp bit must be written to by a program in other than the flash memory. in the following cases, set the fmstp bit to 1 : when flash memory access resulted in an error while erasing or programming in ew0 mode (fmr00 bit not reset to 1 (ready)) when entering on-chip oscillator mode (main clock stop) figure 17.6 shows a flow chart to be followed before and after entering on-chip oscillator mode (main clock stop). note that when going to stop or wait mode while the cpu rewrite mode is disabled, the fmr0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode. fmr06 bit this is a read-only bit indicating the status of auto program operation. the bit is set to 1 when a program error occurs; otherwise, it is cleared to 0 . for details, refer to the description of 17.4.5 full status check . fmr07 bit this is a read-only bit indicating the status of auto erase operation. the bit is set to 1 when an erase error occurs; otherwise, it is set to 0 . for details, refer to the description of 17.4.5 full status check . fmr11 bit setting this bit to 1 (ew1 mode) places the microcomputer in ew1 mode. fmr40 bit the erase-suspend function is enabled by setting the fmr40 bit to 1 (valid). fmr41 bit in ew0 mode, the flash module goes to erase-suspend mode when the fmr41 bit is set to 1 . in ew1 mode, the fmr41 bit is automatically set to 1 (erase-suspend requested) when an enabled interrupt occurred, and then the flash module goes to erase-suspend mode. the auto-erase operation restarts when the fmr41 bit is set to 0 (erase restart). fmr46 bit the fmr46 bit is set to 0 (disables reading) during auto-erase execution and set to 1 (enables reading) during erase-suspend mode. do not access to the flash memory when this bit is set to 0 . 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 170 of 204 rej09b0062-0120 f l a s h m e m o r y c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sa f t e r r e s e t f m r 00 1 b 7 1 6 0 0 0 0 0 0 0 1 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 f m r 0 0 b i t s y m b o l b i t n a m ef u n c t i o nrw 0: busy (being written or erased) 1: ready c p u r e w r i t e m o d e s e l e c t b i t (1 , 6 ) 0: disable cpu rewrite mode 1: enable cpu rewrite mode f m r 0 1 b l o c k 1 , 0 r e w r i t e e n a b l e b i t (2 , 6 ) 0: rewrite disabled 1: rewrite enabled f l a s h m e m o r y s t o p b i t (3 , 5 , 6 ) f m r 0 2 f m s t p 0 ry/by status flag reserved bit set to 0 0: terminated normally 1: terminated in error p r o g r a m s t a t u s f l a g (4 ) f m r 0 6 0: terminated normally 1: terminated in error e r a s e s t a t u s f l a g (4 ) f m r 0 7 rw rw rw rw r o ro ro (b5-b4) 0 : e n a b l e f l a s h m e m o r y o p e r a t i o n 1 : s t o p f l a s h m e m o r y o p e r a t i o n ( p l a c e d i n l o w p o w e r m o d e , f l a s h m e m o r y i n i t i a l i z e d ) n o t e s : 1 . t o s e t t h i s b i t t o 1 , w r i t e 0 a n d t h e n 1 i n s u c c e s s i o n . m a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g 1 a f t e r w r i t i n g 0 . s e t t h e m i c r o c o m p u t e r i n r e a d a r r a y m o d e b e f o r e w r i t i n g 0 t o t h i s b i t . 2 . t o s e t t h i s b i t t o 1 , w r i t e 0 a n d t h e n 1 i n s u c c e s s i o n w h e n t h e f m r 0 1 b i t = 1 . m a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g 1 a f t e r w r i t i n g 0 . 3 . w r i t e t o t h i s b i t f r o m a p r o g r a m i n o t h e r t h a n t h e f l a s h m e m o r y . 4 . t h i s f l a g i s s e t t o 0 b y e x e c u t i n g t h e c l e a r s t a t u s c o m m a n d . 5 . e f f e c t i v e w h e n t h e f m r 0 1 b i t = 1 ( c p u r e w r i t e m o d e ) . i f t h e f m r 0 1 b i t = 0 , a l t h o u g h t h e f m s t p b i t c a n b e s e t t o 1 b y w r i t i n g 1 , t h e f l a s h m e m o r y i s n e i t h e r p l a c e d i n l o w p o w e r m o d e n o r i n i t i a l i z e d . 6 . u s e t h e b i t p r o c e s s i n s t r u c t i o n t o s e t t h e f m r 0 1 , f m r 0 2 a n d f m s t p b i t s ( r e f e r t o r 8 c / t i n y s e r i e s s o f t w a r e m a n u a l . 0 figure 17.3 fmr0 register 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 171 of 204 rej09b0062-0120 figure 17.4 fmr1 register and fmr4 register f l a s h m e m o r y c o n t r o l r e g i s t e r 4 symbol address after reset fmr4 01b3 16 01000000 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 bit symbol b i t n a m ef u n c t i o n erase-suspend request bit (2) 0 : e r a s e r e s t a r t 1 : e r a s e - s u s p e n d r e q u e s t f m r 4 1 0 e r a s e - s u s p e n d f u n c t i o n e n a b l e b i t (1 ) 0 : i n v a l i d 1 : v a l i d r e a d s t a t u s f l a g 0 : d i s a b l e r e a d i n g 1 : e n a b l e r e a d i n g 0 0 r o rw r w r w r w f m r 4 0 fmr46 r e s e r v e d b i t s e t t o 0 ( b 7 ) r e s e r v e d b i t s e t t o 0 (b5-b2) r o n o t e s : 1 . t o s e t t h i s b i t t o 1 , w r i t e 0 a n d t h e n 1 i n s u c c e s s i o n . m a k e s u r e n o i n t e r r u p t s w i l l o c c u r b e f o r e w r i t i n g 1 a f t e r w r i t i n g 0 . 2 . t h i s b i t i s v a l i d o n l y w h e n t h e f m r 4 0 b i t i s s e t t o 1 ( v a l i d ) a n d c a n o n l y b e w r i t t e n b e f o r e e n d i n g a n e r a s e a f t e r i s s u i n g a n e r a s e c o m m a n d . o t h e r t h a n t h i s p e r i o d , t h i s b i t i s s e t t o 0 . i n e w 0 m o d e , t h i s b i t c a n b e s e t t o 0 a n d 1 b y p r o g r a m . i n e w 1 m o d e , t h i s b i t i s a u t o m a t i c a l l y s e t t o 1 i f a m a s k a b l e i n t e r r u p t o c c u r s d u r i n g a n e r a s e o p e r a t i o n w h i l e t h e f m r 4 0 b i t i s s e t t o 1 . t h i s b i t c a n n o t b e s e t t o 1 b y p r o g r a m . ( c a n b e s e t t o 0 . ) 0 0 flash memory control register 1 s y m b o la d d r e s sa f t e r r e s e t f m r 10 1 b 5 1 6 0 1 0 0 x x 0 x 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 bit symbol b i t n a m ef u n c t i o n ew1 mode select bit (1) 0: ew0 mode 1: ew1 mode f m r 1 1 0 reserved bit set to 0 r e s e r v e d b i t when read, its content is indeterminate. reserved bit set to 0 0 0 r w r o r w r w r w (b0) ( b 5 - b 4 ) (b7) reserved bit when read, its content is indeterminate. ( b 3 - b 2 ) ro notes: 1. to set this bit to 1 , write 0 and then 1 in succession when the fmr01 bit = 1. make sure no interrupts will occur before writing 1 after writing 0 . the fmr01 and fmr11 bits both are set to 0 by setting the fmr01 bit to 0 . n o t h i n g i s a s s i g n e d . w h e n w r i t e , s e t t o 0 . (b6) 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 172 of 204 rej09b0062-0120 figure 17.7 setting and resetting of ew1 mode s e t c m 0 a n d c m 1 r e g i s t e r s (1 ) s e t t h e f m r 0 1 b i t b y w r i t i n g 0 a n d t h e n 1 ( c p u r e w r i t e m o d e e n a b l e d ) (2 ) s e t t h e f m r 1 1 b i t b y w r i t i n g 0 a n d t h e n 1 ( e w 1 m o d e ) p r o g r a m i n r o m e w 1 m o d e o p e r a t i o n p r o c e d u r e e x e c u t e s o f t w a r e c o m m a n d s w r i t e 0 t o t h e f m r 0 1 b i t ( c p u r e w r i t e m o d e d i s a b l e d ) notes: 1. select 5 mhz or less for cpu clock using the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register. 2. to set the fmr01 bit to 1 , write 0 and then 1 in succession. make sure no interrupts will occur before writing 1 after writing 0 . execute the read array command (3) s e t c m 0 a n d c m 1 r e g i s t e r s (1 ) execute software commands jump to the rewrite control program which has been transferred to any area other than the flash memory (the subsequent processing is executed by the rewrite control program in any area other than the flash memory) t r a n s f e r a c p u r e w r i t e m o d e b a s e d r e w r i t e c o n t r o l p r o g r a m t o a n y a r e a o t h e r t h a n t h e f l a s h m e m o r y write 0 to the fmr01 bit (cpu rewrite mode disabled) s e t t h e f m r 0 1 b i t b y w r i t i n g 0 a n d t h e n 1 ( c p u r e w r i t e m o d e e n a b l e d ) (2 ) e w 0 m o d e o p e r a t i o n p r o c e d u r e rewrite control program jump to a specified address in the flash memory notes: 1. select 5 mhz or less for cpu clock using the cm06 bit in the cm0 register and the cm17 to cm16 bits in the cm1 register. 2. to set the fmr01 bit to 1 , write 0 and then 1 in succession. make sure no interrupts will occur before writing 1 after writing 0 . write to the fmr01 bit from a program in other than the flash memory. 3. disables the cpu rewrite mode after executing the read array command. figure 17.6 setting and resetting of ew0 mode figures 17.6 and 17.7 show the setting and resetting of ew0 mode and ew1 mode, respectively. 17.4 cpu rewrite mode during erase erase starts fmr00 fmr46 erase suspends erase starts check that the fmr00 bit is set to 0 , and that the erase operation has not ended. check the status, and that the program ends normally. erase ends during erase figures 17.5 shows the timing on suspend operation. figure 17.5 timing on suspend operation
r8c/11 group rev.1.20 jan 27, 2006 page 173 of 204 rej09b0062-0120 figure 17.8 process to reduce power consumption in on-chip oscillator mode (main clock stop) t u r n m a i n c l o c k o n t r a n s f e r o n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p ) p r o g r a m t o a n y a r e a o t h e r t h e f l a s h m e m o r y s w i t c h t h e c l o c k s o u r c e f o r c p u c l o c k . t u r n x i n o f f j u m p t o t h e o n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p ) p r o g r a m w h i c h h a s b e e n t r a n s f e r r e d t o a n y a r e a o t h e r t h e f l a s h m e m o r y . ( t h e s u b s e q u e n t p r o c e s s i n g i s e x e c u t e d b y a p r o g r a m i n a n y a r e a o t h e r t h a n t h e f l a s h m e m o r y . ) w a i t u n t i l t h e f l a s h m e m o r y c i r c u i t s t a b i l i z e s ( 1 5 0 ( f l a s h m e m o r y o p e r a t i o n ) (4 ) s e t f m s t p b i t t o 1 ( f l a s h m e m o r y s t o p p e d . l o w p o w e r s t a t e ) (1 ) p r o c e s s o f o n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p ) s w i t c h t h e c l o c k s o u r c e f o r c p u c l o c k (2 ) o n - c h i p o s c i l l a t o r m o d e ( m a i n c l o c k s t o p ) p r o g r a m w r i t e 0 t o t h e f m r 0 1 b i t ( c p u r e w r i t e m o d e d i s a b l e d ) s e t t h e f m r 0 1 b i t b y w r i t i n g 0 a n d t h e n 1 ( c p u r e w r i t e m o d e e n a b l e d ) j u m p t o a s p e c i f i e d a d d r e s s i n t h e f l a s h m e m o r y w a i t u n t i l o s c i l l a t i o n s t a b i l i z e s n o t e s : 1 . s e t t h e f m r 0 1 b i t t o 1 ( c p u r e w r i t e m o d e ) b e f o r e s e t t i n g t h e f m s t p b i t t o 1 . 2 . b e f o r e t h e c l o c k s o u r c e f o r c p u c l o c k c a n b e c h a n g e d , t h e c l o c k t o w h i c h t o b e c h a n g e d m u s t b e s t a b l e . 3 . i n s e r t a 1 5 s w a i t t i m e i n a p r o g r a m . a v o i d a c c e s s i n g t o t h e f l a s h m e m o r y d u r i n g t h i s w a i t t i m e . 4 . e n s u r e 1 0 s u n t i l s e t t i n g 0 ( f l a s h m e m o r y o p e r a t e s ) a f t e r s e t t i n g t h e f m s t p b i t t o 1 ( f l a s h m e m o r y s t o p s ) . 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 174 of 204 rej09b0062-0120 read array command this command reads the flash memory. writing ff 16 in the first bus cycle places the microcomputer in read array mode. enter the read address in the next or subsequent bus cycles, and the content of the specified address can be read in 8-bit units. because the microcomputer remains in read array mode until another command is written, the con- tents of multiple addresses can be read in succession. read status register command this command reads the status register. write 70 16 in the first bus cycle, and the status register can be read in the second bus cycle. (refer to section 17.4.4, status register. ) when reading the status register too, specify an address in the user rom area. avoid executing this command in ew1 mode. clear status register command this command sets the status register to 0 . write 50 16 in the first bus cycle, and the fmr06 to fmr07 bits in the fmr0 register and sr4 to sr5 in the status register will be set to 0 . command program clear status register read array read status register first bus cycle second bus cycle block erase write write write write write mode read write write mode x wa ba address srd wd d0 16 data (d 7 to d 0 ) ff 16 70 16 50 16 40 16 20 16 data (d 7 to d 0 ) x x x wa x address srd: status register data (d 7 to d 0 ) wa: write address (make sure the address value specified in the the first bus cycle is the same address as the write address specified in the second bus cycle.) wd: write data (8 bits) ba: given block address x: any address in the user rom area 17.4.3 software commands software commands are described below. the command code and data must be read and written in 8-bit units. table 17.4 software commands 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 175 of 204 rej09b0062-0120 start program completed yes no write the command code 40 16 to the write address write data to the write address fmr00=1? full status check figure 17.9 program command program command this command writes data to the flash memory in one byte units. write 40 16 in the first bus cycle and write data to the write address in the second bus cycle, and an auto program operation (data program and verify) will start. make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. check the fmr00 bit in the fmr0 register to see if auto programming has finished. the fmr00 bit is 0 during auto programming and set to 1 when auto programming is completed. check the fmr06 bit in the fmr0 register after auto programming has finished, and the result of auto programming can be known. (refer to section 17.4.5, full status check. ) writing over already programmed addresses is inhibited. when the fmr02 bit in the fmr0 register is set to 0 (rewrite disabled), the program command on the block0 and block1 is not accepted. in ew1 mode, do not execute this command on any address at which the rewrite control program is located. in ew0 mode, the microcomputer goes to read status register mode at the same time auto program- ming starts, making it possible to read the status register. the status register bit 7 (sr7) is set to 0 at the same time auto programming starts, and set back to 1 when auto programming finishes. in this case, the microcomputer remains in read status register mode until a read array command is written next. the result of auto programming can be known by reading the status register after auto programming has finished. 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 176 of 204 rej09b0062-0120 write d0 16 to the given block address start block erase completed yes no write the command code 20 16 fmr00=1? full status check figure 17.10 block erase command (when not using erase-suspend function) block erase write 20 16 in the first bus cycle and write d0 16 to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. check the fmr00 bit in the fmr0 register to see if auto erasing has finished. the fmr00 bit is 0 during auto erasing and set to 1 when auto erasing is completed. check the fmr07 bit in the fmr0 register after auto erasing has finished, and the result of auto erasing can be known. (refer to section 17.4.5, full status check. ) when the fmr02 bit in the fmr0 register is set to 0 (rewrite disabled), the block erase command on the block0 and block1 is not accepted. figure 17.10 shows an example of a block erase flowchart when the erase-suspend function is not used. figure 17.11 shows an example of a block erase flowchart when the erase-suspend function is used. in ew1 mode, do not execute this command on any address at which the rewrite control program is located. in ew0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making it possible to read the status register. the status register bit 7 (sr7) is cleared to 0 at the same time auto erasing starts, and set back to 1 when auto erasing finishes. in this case, the microcomputer remains in read status register mode until the read array command is written next. 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 177 of 204 rej09b0062-0120 figure 17.11 block erase flow chart (when using erase-suspend function) w r i t e d 0 1 6 t o t h e a n y b l o c k a d d r e s s s t a r t block erase completed y e s n o w r i t e t h e c o m m a n d c o d e 2 0 1 6 f m r 0 0 = 1 ? full status check i n t e r r u p t (1 , 2 ) reit y e s n o f m r 4 6 = 1 ? a c c e s s t o f l a s h m e m o r y f m r 4 0 = 1 f m r 4 0 = 1 f m r 4 1 = 0 < e w 0 m o d e > write d0 16 to the any block address s t a r t write the command code 20 16 b l o c k e r a s e c o m p l e t e d y e s no f m r 0 0 = 1 ? f u l l s t a t u s c h e c k i n t e r r u p t (2 ) r e i t a c c e s s t o f l a s h m e m o r y f m r 4 0 = 1 < e w 1 m o d e > f m r 4 1 = 0 notes: 1. in ew0 mode, interrupt vector table and interrupt routine for an interrupt used should be located in the ram space. 2. td(sr-es) is needed after an interrupt request is generated before being acknowledged. the interrupt to enter an erase-suspend should be in interrupt enabled status. 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 178 of 204 rej09b0062-0120 17.4.4 status register the status register indicates the operating status of the flash memory and whether an erase or pro- gramming operation terminated normally or in error. the status of the status register can be known by reading the fmr00, fmr06, and fmr07 bits in the fmr0 register. table 17.5 lists the status register. in ew0 mode, the status register can be read in the following cases: (1) when a given address in the user rom area is read after writing the read status register com- mand (2) when a given address in the user rom area is read after executing the program or block erase command but before executing the read array command. sequence status (sr7 and fmr00 bits ) the sequence status indicates the operating status of the flash memory. sr7 = 0 (busy) during auto programming and auto erase, and is set to 1 (ready) at the same time the operation finishes. erase status (sr5 and fmr07 bits) refer to section 17.4.5, full status check. program status (sr4 and fmr06 bits) refer to section 17.4.5, full status check. table 17.5 status register status register bit sr4 (d 4 ) sr5 (d 5 ) sr7 (d 7 ) sr6 (d 6 ) status name contents sr1 (d 1 ) sr2 (d 2 ) sr3 (d 3 ) sr0 (d 0 ) program status erase status sequencer status reserved reserved reserved reserved "1" ready terminated in error terminated in error - - - - - "0" busy terminated normally terminated normally - - - - - reserved fmr0 register bit fmr00 fmr07 fmr06 value after reset 1 0 0 d 7 to d 0 : indicates the data bus which is read out when the read status register command is executed. the fmr07 bit (sr5) and fmr06 bit (sr4) are set to 0 by executing the clear status register com- mand. when the fmr07 bit (sr5) or fmr06 bit (sr4) = 1, the program and block erase commands are not accepted. 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 179 of 204 rej09b0062-0120 17.4.5 full status check when an error occurs, the fmr06 to fmr07 bits in the fmr0 register are set to 1 , indicating occur- rence of each specific error. therefore, execution results can be verified by checking these status bits (full status check). table 17.6 lists errors and fmr0 register status. figure 17.12 shows a full status check flowchart and the action to be taken when each error occurs. table 17.6 errors and fmr0 register status frm00 register (status register) status error error occurrence condition fmr07 fmr06 (sr5) (sr4) 1 1 command when any command is not written correctly sequence error when invalid data was written other than those that can be writ- ten in the second bus cycle of the block erase command (i.e., other than d0 16 or ff 16 ) (1) when executing the program command or block erase command while rewriting is disabled using the fmr02 bit in the fmr0 regis- ter, the fmr15 or fmr16 bit in the fmr1 register. when inputting and erasing the address in which the flash memory is not allocated during the erase command input. when executing to erase the block which disables rewriting dur- ing the erase command input. when inputting and writing the address in which the flash memory is not allocated during the write command input. when executing to write the block which disables rewriting during the write command input. 1 0 erase error when the block erase command was executed but not automati- cally erased correctly 0 1 program error when the program command was executed but not automatically programmed correctly. notes: 1. writing ff 16 in the second bus cycle of these commands places the microcomputer in read array mode, and the command code written in the first bus cycle is nullified. 17.4 cpu rewrite mode
r8c/11 group rev.1.20 jan 27, 2006 page 180 of 204 rej09b0062-0120 f u l l s t a t u s c h e c k f m r 0 6 = 1 a n d f m r 0 7 = 1 ? n o y e s fmr07=0? n o y e s n o t e s : 1 . t o r e w r i t e t o t h e a d d r e s s w h e r e t h e p r o g r a m e r r o r o c c u r s , c h e c k i f t h e f u l l s t a t u s c h e c k i s c o m p l e t e n o r m a l l y a n d w r i t e t o t h e a d d r e s s a f t e r t h e b l o c k e r a s e c o m m a n d i s e x e c u t e d . fmr06=0? no yes full status check completed c o m m a n d s e q u e n c e e r r o r e r a s e e r r o r p r o g r a m e r r o r c o m m a n d s e q u e n c e e r r o r e r a s e e r r o r e x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( s e t t h e s e s t a t u s f l a g s t o 0 ) c h e c k i f c o m m a n d i s p r o p e r l y i n p u t r e - e x e c u t e t h e c o m m a n d e x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( s e t t h e s e s t a t u s f l a g s t o 0 ) erase command re-execution times figure 17.12 full status check and handling procedure for each error 17.4 cpu rewrite mode
r8c/11 group 17.5 standard serial i/o mode rev.1.20 jan 27, 2006 page 181 of 204 rej09b0062-0120 17.5 standard serial i/o mode in standard serial i/o mode, the user rom area can be rewritten while the microcomputer is mounted on- board by using a serial programmer suitable for this microcomputer. standard serial i/o mode has stan- dard serial i/o mode 1 of the clock synchronous serial and standard serial i/o mode 2 of the clock asynchronous serial. refer to "appendix 2 connecting examples for serial writer and on-chip debug- ging emulator". for more information about serial programmers, contact the manufacturer of your serial programmer. for details on how to use, refer to the user s manual included with your serial programmer. table 17.7 lists pin functions (flash memory standard serial input/output mode). figures 17.13 to 17.15 show pin connections for standard serial i/o mode. 17.5.1 id code check function this function determines whether the id codes sent from the serial programmer and those written in the flash memory match (refer to section 17.3, functions to prevent flash memory from rewriting ).
r8c/11 group 17.5 standard serial i/o mode rev.1.20 jan 27, 2006 page 182 of 204 rej09b0062-0120 p i n d e s c r i p t i o n v cc ,v ss apply the voltage guaranteed for program and erase to vcc pin and 0v to vss pin. iv cc c o n n e c t c a p a c i t o r ( 0 . 1 f ) t o v s s . reset p4 6 /x in connect a ceramic resonator or crystal oscillator between x in and x out pins in standard serial i/o mode 2. when using the main clock in standard serial i/o mode 1, connect a ceramic resonator or crystal oscillator between x in and x out pins. when not using the main clock in standard serial i/o mode 1, connect this pin to vcc via a resistor(pull-up) p4 7 /x out av cc , av ss v ref c o n n e c t a v s s t o v s s a n d a v c c t o v c c , r e s p e c t i v e l y . e n t e r t h e r e f e r e n c e v o l t a g e f o r a d f r o m t h i s p i n . p0 1 to p0 7 i n p u t " h " o r " l " l e v e l s i g n a l o r o p e n . p1 0 to p1 7 i n p u t " h " o r " l " l e v e l s i g n a l o r o p e n . p3 0 to p3 3 i n p u t " h " o r " l " l e v e l s i g n a l o r o p e n . p4 5 i n p u t " h " o r " l " l e v e l s i g n a l o r o p e n . p0 0 s e r i a l d a t a o u t p u t p i n mode cnv ss s t a n d a r d s e r i a l i / o m o d e 1 : c o n n e c t t o f l a s h p r o g r a m m e r s t a n d a r d s e r i a l i / o m o d e 2 : i n p u t " l " . p3 7 serial data input pin n a m e p o w e r i n p u t i v c c r e s e t i n p u t p 4 6 i n p u t / c l o c k i n p u t p 4 7 i n p u t / c l o c k o u t p u t a n a l o g p o w e r s u p p l y i n p u t r e f e r e n c e v o l t a g e i n p u t i n p u t p o r t p 0 i n p u t p o r t p 1 i n p u t p o r t p 3 i n p u t p o r t p 4 t x d o u t p u t mode c n v s s rxd input i / o i i i / o i i i i i o i / o i / o i s t a n d a r d s e r i a l i / o m o d e 1 : c o n n e c t t o f l a s h p r o g r a m m e r s t a n d a r d s e r i a l i / o m o d e 2 : i n p u t " l " . r e s e t i n p u t p i n . i table 17.7 pin functions (flash memory standard serial i/o mode)
r8c/11 group 17.5 standard serial i/o mode rev.1.20 jan 27, 2006 page 183 of 204 rej09b0062-0120 figure 17.13 pin connections for standard serial i/o mode c o n n e c t o s c i l l a t o r c i r c u i t (1 ) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r 8 c / 1 1 v c c vss r x d c n v s s r e s e t t x d m o d e notes: 1: no need to connect an oscillation circuit when operating with on-chip oscillator clock . c n v s s vss -->vcc r e s e t mode rxd mode setting s i g n a l value v o l t a g e f r o m p r o g r a m m e r v o l t a g e f r o m p r o g r a m m e r voltage from programmer package: plqp0032gb-a (32p6u-a)
r8c/11 group 17.5 standard serial i/o mode rev.1.20 jan 27, 2006 page 184 of 204 rej09b0062-0120 data input data output txd cnvss rxd microcomputer (1) in this example, modes are switched between single-chip mode and standard serial i/o mode by controlling the mode input with a switch. (2) connecting the oscillation is necessary. set the main clock frequency 1mhz to 20 mhz. refer to "appendix 2.2 connecting examples with m16c flash starter (m3a-0806)". mode example of circuit application in the standard serial i/o mode figures 17.14 and 17.15 show examples of circuit application in standard serial i/o mode 1 and mode 2, respectively. refer to the serial programmer manual of your programmer to handle pins controlled by the programmer. figure 17.14 circuit application in standard serial i/o mode 1 mode i/o data output cnvss input data input txd mode cnvss reset rxd reset input user reset signal microcomputer (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. (2) in this example, modes are switched between single-chip mode and standard serial input/output mode by connecting a programmer. (3) when operating with the on-chip oscillator clock, connecting the oscillation circuit is not necessary. refer to "appendix figure 2.1 connecting examples with usb flash writer ( m3a-0665 ) ". figure 17.15 circuit application in standard serial i/o mode 2
r8c/11 group 18. on-chip debugger rev.1.20 jan 27, 2006 page 185 of 204 rej09b0062-0120 18. on-chip debugger the microcomputer has functions to execute the on-chip debugger. refer to "appendix 2 connecting examples for serial writer and on-chip debugging emulator". refer to the respective on-chip debugger manual for the details of the on-chip debugger. next, here are some explanations for the respective functions. debugging the user system which uses these functions is not available. when using the on- chip debugger, design the system without using these functions in advance. additionally, the on-chip debugger uses the address 0c000 16 to 0c7ff 16 of the flash memory, thus avoid using for the user system. 18.1 address match interrupt the interrupt request is generated right before the arbitrary address instruction is executed. the debugger break function uses the address match interrupt. refer to "10.4 address match interrupt" for the details of the address match interrupt. also, avoid setting the address match interrupt (the registers of aier, rmad0, rmad1 and the fixed vector tables) with using the user system when using the on-chip debugger. 18.2 single step interrupt the interrupt request is generated every time one instruction is executed. the debugger single step function uses the single step interrupt. the other interrupt is not generated when using the single step interrupt. the single step interrupt is only for the developed support tool. 18.3 uart1 the uart1 is used for the communication with the debugger (or the personal computer). refer to "13. serial interface" for the details of uart1. also, avoid using the uart1 and the functions (p0 0 /an 7 and p3 7 ) which share the uart1 pins. 18.4 brk instruction the brk interrupt request is generated. refer to "10.1 interrupt overview" and "r8c/tiny series soft- ware manual". also, avoid using the brk instruction with using the user system when using the on-chip debugger.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 186 of 204 rej09b0062-0120 19. usage notes 19.1 stop mode and wait mode 19.1.1 stop mode when entering stop mode, set the cm10 bit to 1 (stop mode) after setting the fmr01 bit to 0 (cpu rewrite mode disabled). the instruction queue pre-reads 4 bytes from the instruction which sets the cm10 bit in the cm1 register to 1 (stop mode) and the program stops. insert at least 4 nop instruc- tions after inserting the jmp.b instruction immediately after the instruction which sets the cm10 bit to 1 . use the next program to enter stop mode. program of entering stop mode bclr 1, fmr0 ; cpu rewrite mode disabled bset 0, prcr ; protect exited bset 0, cm1 ; stop mode jmp.b label_001 label_001: nop nop nop nop 19.1.2 wait mode when entering wait mode, execute the wait instruction after setting the fmr01 bit to 0 (cpu re- write mode disabled). the instruction queue pre-reads 4 bytes from the wait instruction and the program stops. insert at least 4 nop instructions after the wait instruction. also, the value in the specific internal ram area may be rewritten when exiting wait mode if writing to the interna ram area before executing the wait instruction and entering wait mode. the area for a maximum of 3 bytes is rewirtten from the following address of the internal ram in which the writing is performed before the wait instruction. if this causes a problem, avoid by inserting the jmp.b instruc- tion between the writing instruction to the internal ram area and wait instruction as shown in the following program example. example to execute wait instruction program example mov.b #055h,0601h ; write to internal ram area jmp.b label_001 label_001 : fset i ; interrupt enabled bclr 1,fmr0 ; cpu rewrite mode disabled wait ; wait mode nop nop nop nop when accessing any area other than the internal ram area between the writing instruction to the internal ram area and execution of the wait instruction, this situation will not occur.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 187 of 204 rej09b0062-0120 19.2 interrupt 19.2.1 reading address 00000 16 do not read the address 00000 16 by a program. when a maskable interrupt request is acknowledged, the cpu reads interrupt information (interrupt number and interrupt request level) from 00000 16 in the interrupt sequence. at this time, the acknowledged interrupt ir bit is set to 0 . if the address 00000 16 is read by a program, the ir bit for the interrupt which has the highest priority among the enabled interrupts is set to 0 . this may cause a problem that the interrupt is canceled, or an unexpected interrupt is generated. 19.2.2 sp setting set any value in the sp before an interrupt is acknowledged. the sp is set to 0000 16 after reset. therefore, if an interrupt is acknowledged before setting any value in the sp, the program may run out of control. 19.2.3 external interrupt and key input interrupt ________ either an l level or an h level of at least 250ns width is necessary for the signal input to the int 0 to ________ _____ _____ int 3 pins and ki 0 to ki 3 pins regardless of the cpu clock. 19.2.4 watchdog timer interrupt reset the watchdog timer after a watchdog timer interrupt is generated.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 188 of 204 rej09b0062-0120 figure 19.1 example of procedure for changing interrupt factor d i s a b l e i n t e r r u p t (2 , 3 ) c h a n g e i n t e r r u p t f a c t o r ( i n c l u d i n g m o d e o f p e r i p h e r a l f u n c t i o n s ) e n a b l e i n t e r r u p t (2 , 3 ) i n t e r r u p t f a c t o r c h a n g e change completed i r b i t : t h e i n t e r r u p t c o n t r o l r e g i s t e r b i t o f a n i n t e r r u p t w h o s e f a c t o r i s c h a n g e d n o t e s : 1 . e x e c u t e t h e a b o v e s e t t i n g i n d i v i d u a l l y . d o n o t e x e c u t e t w o o r m o r e s e t t i n g s a t o n c e ( b y o n e i n s t r u c t i o n ) . 2 . u s e t h e i f l a g f o r t h e i n t i ( i = 0 t o 3 ) i n t e r r u p t . t o p r e v e n t i n t e r r u p t r e q u e s t s f r o m b e i n g g e n e r a t e d w h e n u s i n g p e r i p h e r a l f u n c t i o n i n t e r r u p t s o t h e r t h a n t h e i n t i i n t e r r u p t f a c t o r . i n t h i s c a s e , u s e t h e i f l a g w h e n a l l m a s k a b l e i n t e r r u p t s c a n b e d i s a b l e d . w h e n a l l m a s k a b l e i n t e r r u p t s c a n n o t b e d i s a b l e d , u s e t h e i l v l 0 t o i l v l 2 b i t s o f t h e i n t e r r u p t w h o s e f a c t o r i s c h a n g e d . 3 . r e f e r t o 1 9 . 2 . 6 c h a n g i n g i n t e r r u p t c o n t r o l r e g i s t e r f o r t h e i n s t r u c t i o n s t o b e u s e d a n d t h e i r u s a g e n o t e s . s e t i r b i t t o 0 ( i n t e r r u p t n o t r e q u e s t e d ) u s i n g m o v i n s t r u c t i o n (3 ) 19.2.5 changing interrupt factor the ir bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt factor is changed. when using an interrupt, set the ir bit to 0 (interrupt not request) after changing the interrupt factor. in addition, the changes of interrupt factors include all elements that change the interrupt factors assigned to individual software interrupt numbers, polarities, and timing. therefore, when a mode change of the peripheral functions involves interrupt factors, edge polarities, and timing, set the ir bit to 0 (interrupt not requested) after the change. refer to each peripheral function for the interrupts caused by the peripheral functions. figure 19.1 shows an example of procedure for changing interrupt factor.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 189 of 204 rej09b0062-0120 example 1: use nop instructions to prevent i flag being set to 1 before interrupt control register is changed int_switch1: fclr i ; disable interrupts and.b #00h, 0056h ; set txic register to 00 16 nop nop fset i ; enable interrupts example 2: use dummy read to have fset instruction wait int_switch2: fclr i ; disable interrupts and.b #00h, 0056h ; set txic register to 00 16 mov.w mem, r0 ; dummy read fset i ; enable interrupts example 3: use popc instruction to change i flag int_switch3: pushc flg fclr i ; disable interrupts and.b #00h, 0056h ; set txic register to 00 16 popc flg ; enable interrupts 19.2.6 changing interrupt control register (1) each interrupt control register can only be changed while interrupt requests corresponding to that register are not generated. if interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (2) when changing any interrupt control register after disabling interrupts, be careful with the instruc- tion to be used. when changing any bit other than ir bit if an interrupt request corresponding to that register is generated while executing the instruction, the ir bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. if this causes a problem, use the following instructions to change the register. instructions to use: and, or, bclr, bset when changing ir bit if the ir bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. use the mov instruction to set the ir bit to 0 . (3) when disabling interrupts using the i flag, set the i flag according to the following sample pro- grams. refer to (2) for the change of interrupt control registers in the sample programs. sample programs 1 to 3 are preventing the i flag from being set to 1 (interrupt enabled) before writing to the interrupt control registers for reasons of the internal bus or the instruction queue buffer.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 190 of 204 rej09b0062-0120 19.3 clock generation circuit 19.3.1 oscillation stop detection function since the oscillation stop detection function cannot be used if the main clock frequency is below 2mhz, set the ocd1 to ocd0 bits to 00 2 (oscillation stop detection function disabled). 19.3.2 oscillation circuit constants ask the maker of the oscillator to specify the best oscillation circuit constants on your system.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 191 of 204 rej09b0062-0120 19.4 timers 19.4.1 timers x, y and z (1) timers x, y and z stop counting after reset. therefore, a value must be set to these timers and prescalers before starting counting. (2) even if the prescalers and timers are read out simultaneously in 16-bit units, these registers are read byte-by-byte in the microcomputer. consequently, the timer value may be updated during the period these two registers are being read. 19.4.2 timer x (1) do not rewrite the txmod0 to txmod1 bits, the txmod2 bit and txs bit simultaneously. (2) in pulse period measurement mode, the txedg bit and txund bit in the txmr register can be set to 0 by writing 0 to these bits in a program. however, these bits remain unchanged when 1 is written. to set one flag to 0 in a program, write "1" to the other flag by using the mov instruction. (this prevents any unintended changes of flag.) example (when setting txedg bit to 0 ): mov.b #10xxxxxxb,008bh (3) w hen changing to pulse period measurement mode from other mode, the contents of the txedg bit and txund bit are indeterminate. write "0" to the txedg bit and txund bit before starting counting. (4) the prescaler x underflow which is generated for the first time after the count start may cause that the txedg bit is set to 1 . when using the pulse period measurement mode, leave more than two periods of the prescaler x right after count starts and set the txedg bit to 0 . 19.4.3 timer y (1) do not rewrite the tymod0 and tys bits simultaneously. 19.4.4 timer z (1) do not rewrite the tzmod0 to tzmod1 bits and the tzs bit simultaneously. (2) in programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the tzs bit in the tc register to 0 (stops counting) or setting the tzos bit in the tzoc register to 0 (stops one-shot), the timer reloads the value of reload register and stops. therefore, the timer count value should be read out in programmable one-shot generation mode and programmable wait one-shot generation mode before the timer stops. 19.4.5 timer c (1) access the tc, tm0 and tm1 registers in 16-bit units. this prevents the timer value from being updated between the low-order byte and high-order byte are being read. example (when timer c is read): mov.w 0090h,r0 ; read out timer c
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 192 of 204 rej09b0062-0120 19.5 serial interface (1) when reading data from the uirb (i=0,1) register even in the clock asynchronous serial i/o mode or in the clock synchronous serial i/o mode. be sure to read data in 16-bit unit. when the high-byte of the uirb register is read, the per and fer bits of the uirb register and the ri bit of the uic1 register are set to "0". example (when reading receive buffer register): mov.w 00a6h, r0 ; read the u0rb register (2) when writing data to the uitb register in the clock asynchronous serial i/o mode with 9-bit transfer data length, data should be written high-byte first then low-byte in 8-bit unit. example (when reading transmit buffer register): mov.b #xxh, 00a3h ; write the high-byte of u0tb register mov.b #xxh, 00a2h ; write the low-byte of u0tb register
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 193 of 204 rej09b0062-0120 19.6 a/d converter (1) when writing to each bit but except bit 6 in the adcon0 register, each bit in the adcon1 register, or the smp bit in the adcon2 register, a/d conversion must be stopped (before a trigger occurs). when the vcut bit in the adcon1 register is changed from 0 (v ref not connected) to 1 (v ref connected), wait at least 1 ? before starting a/d conversion. (2) when changing ad operation mode, select an analog input pin again. (3) in one-shot mode, a/d conversion must be completed before reading the ad register. the ir bit in the adic register or the adst bit in the adcon0 register can indicates whether the a/d conversion is completed or not. (4) in repeat mode, the undivided main clock must be used for the cpu clock. (5) if a/d conversion is forcibly terminated while in progress by setting the adst bit in the adcon0 register to 0 (a/d conversion halted), the conversion result of the a/d converter is indeterminate. if the adst bit is set to 0 in a program, ignore the value of ad register. (6) a 0.1 ? capacitor should be connected between the avcc/v ref pin and avss pin.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 194 of 204 rej09b0062-0120 19.7 flash memory version 19.7.1 cpu rewrite mode 0 to the corresponding bits before writing 1 when setting the fmr01, fmr02, and fmr11 bits to 1 . do not generate an interrupt between writing 0 and 1 . 1 (flash memory stops) during erase suspend in ew1 mode, do not set the fmstp bit to 1 .
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 195 of 204 rej09b0062-0120
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 196 of 204 rej09b0062-0120 mode ew1 status during auto- matic erasing (erase-sus- pend func- tion is en- abled) when maskable interrupt request is acknowledged the auto-erasing is sus- pended and the interrupt pro- cess is executed. the auto- erasing can be restarted by setting the fmr41 bit in the fmr4 register to 0 (erase restart) after the interrupt process completes the auto-erasing has a prior- ity and the interrupt request acknowledgement is waited. the interrupt process is ex- ecuted after the auto-erasing completes the auto-programming has a priority and the interrupt re- quest acknowledgement is waited. the interrupt process is executed after the auto- programming completes when watchdog timer, oscillation stop detection and voltage detection interrupt request area acknowledged once an interrupt request is acknowledged, the auto-programming or auto-erasing is forc- ibly stopped and resets the flash memory. an interrupt process starts after the fixed period and the flash memory restarts. since the block during the auto-erasing or the address during the auto-programming is forcibly stopped, the normal value may not be read. execute the auto-erasing again and ensure the auto-eras- ing is competed normally. since the watchdog timer does not stop during the command op- eration, the interrupt request may be gener- ated. reset the watchdog timer regularly using the erase-suspend function. table 19.2 interrupt in ew1 mode during auto- matic erasing (erase-sus- pend func- tion is dis- abled) auto pro- gramming notes: 1. do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on rom. 2. do not use the non-maskable interrupt while block 0 is automatically erased because the fixed bector is allocated block 0.
r8c/11 group 19. usage notes rev.1.20 jan 27, 2006 page 197 of 204 rej09b0062-0120 19.8 noise (1) bypass capacitor between v cc and v ss pins insert a bypass capacitor (at least 0.1 f) between v cc and v ss pins as the countermeasures against noise and latch-up. the connecting wires must be the shortest and widest possible. (2) port control registers data read error during severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may changed. as a firmware countermeasure, it is recommended to periodically reset the port registers, port direction registers and pull-up control registers. however, you should fully examine before introducing the reset routine as conflicts may be created between this reset routine and interrupt routines (i. e. ports are switched during interrupts). (3) cnvss pin wiring in order to improve the pin tolerance to noise, insert a pull down resistance (about 5 k ?
r8c/11 group 20. usage notes for on-chip debugger rev.1.20 jan 27, 2006 page 198 of 204 rej09b0062-0120 20. usage notes for on-chip debugger when using the on-chip debugger to develop the r8c/11 group program and debug, pay the following attention. (1) do not use p0 0 /an 7 /txd 11 pin and p3 7 /txd 10 /rxd 1 pin. (2) when write in the pd3 register (00e7 16 address), set bit 7 to "0". (3) do not access the related serial interface1 register. (4) do not use from oc000 16 address to oc7ff 16 address because the on-chip debagger uses these addresses. (5) do not set the address match interrupt (the registers of aier, rmad0, rmad1 and the fixed vector tables) in a user system. (6) do not use the brk instruction in a user system. (7) do not set the b5 to 0 by a user program since the on-chip debugger uses after setting the b5 in the fmr0 register to 1 . (8) the stack pointer with up to 8 bytes is used during the user program break. therefore, save space of 8 bytes for the stack area. connecting and using the on-chip debugger has some peculiar restrictions. refer to each on-chip debugger manual for on-chip debugger details.
r8c/11 group appendix 1. package dimensions rev.1.20 jan 27, 2006 page 199 of 204 rej09b0062-0120 appendix 1. package dimensions 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c
r8c/11 group appendix 2. connecting examples for serial writer and on-chip debugging emulator rev.1.20 jan 27, 2006 page 200 of 204 rej09b0062-0120 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r 8 c / 1 1 v c c vss r x d c o n n e c t o s c i l l a t o r c i r c u i t (1 ) c n v s s t x d m o d e notes: 1. no need to connect an oscillation circuit when operating with on-chip oscillator clock . u s e r r e s e t s i g n a l 1 0 t x d 8 r e s e t rxd mode 4 2 v c c 1 cnvss 3 v s s 7 usb flash writer (m3a-0665) 3 3 k ? appendix 2. connecting examples for serial writer and on-chip debugging emulator appendix figure 2.1 shows connecting examples with usb flash writer and appendix figure 2.2 shows connecting examples with m16c flash starter. appendix figure 2.1 connecting examples with usb flash writer (m3a-0665) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r 8 c / 1 1 v c c vss r x d c o n n e t o s c i l l a t o r c i r c u i t (1 ) c n v s s t x d m o d e n o t e s : 1 .n e e d t o c o n n e c t t h e o s c i l l a t o r c i r c u i t , e v e n w h e n o p e r a t i n g w i t h t h e o n - c h i p o s c i l l a t o r c l o c k . 1 0 t x d rxd 4 v c c 1 v s s 7 m 1 6 c f l a s h s t a r t e r ( m 3 a - 0 8 0 6 ) r e s e t appendix figure 2.2 connecting examples with m16c flash starter (m3a-0806)
r8c/11 group appendix 2. connecting examples for serial writer and on-chip debugging emulator rev.1.20 jan 27, 2006 page 201 of 204 rej09b0062-0120 appendix figure 2.3 shows connecting examples with emulator e7. 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r 8 c / 1 1 vcc v s s r x d connect oscillator circuit (1) t x d m o d e notes: 1. no need to connect an oscillation circuit when operating with on-chip oscillator clock. user reset si g nal t x d reset r x d m o d e 4 2 v c c 1 c n v s s 5 v s s c n v s s e m u l a t o r e 7 ( h s 0 0 0 7 t c u 0 1 h ) 8 6 1 0 1 2 1 4 7 1 3 1 1 appendix figure 2.3 connecting examples with emulator e7 (hs0007tcu01h )
r8c/11 group appendix 3. package dimensions rev.1.20 jan 27, 2006 page 202 of 204 rej09b0062-0120 appendix 3. example of oscillation evaluation circuit appendix figure 3.1 shows the example of oscillation evaluation circuit. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 r8c/10 group vcc vss connect oscillation circuit reset 0.1 f notes: 1. set a program before evaluating. appendix figure 3.1 example of oscillation evaluation circuit
r8c/11 group register index rev.1.20 jan 27, 2006 page 203 of 204 rej09b0062-0120 register index a ad 127 adcon0 126, 129, 131 adcon1 126, 129, 131 adcon2 127 adic 53 aier 67 c cm0 31 cm1 31 cmp0ic 53 cmp1ic 53 cmp2ic 53 d d4int 23 drr 144 f fmr0 170 fmr1 171 fmr4 171 h hr0 33 hr1 33 i int0f 60 int0ic 53 int1ic 53 int2ic 53 int3ic 53 inten 60 k kien 65 kupic 53 o ocd 32 p p0 143 p1 143 p3 144 p4 143 pd0 143 pd1 143 pd3 143 pd4 143 pm0 45 pm1 45 prcr 44 prex 72 prey 81 prez 89 pum 82, 84, 86, 90, 92, 94, 96, 99 pur0 144 pur1 144 r rmad0 67 rmad1 67 s s0ric 53 s0tic 53 s1ric 53 s1tic 53 t tc 103 tcc0 64, 103 tcc1 64, 104 tcic 53 tcout 104 tcss 72, 82, 90 tm0 103
r8c/11 group register index rev.1.20 jan 27, 2006 page 204 of 204 rej09b0062-0120 tm1 103 tx 72 txic 53 txmr 62, 71, 73, 74, 75, 76, 78 tyic 53 typr 81 tysc 81 tyzmr 62, 80, 84, 86, 88, 92, 94, 96, 99 tyzoc 81, 89 tzic 53 tzpr 89 tzsc 89 u u0brg 111 u0c0 112 u0c1 113 u0mr 112 u0rb 111 u0tb 111 u1brg 111 u1c0 112 u1c1 113 u1mr 112 u1rb 111 u1tb 111 ucon 113 v vcr1 22 vcr2 22 w wdc 69 wdtr 69 wdts 69
c-1 revision history rev. date description page summary r8c/11 group hardware manual 0.91 sep 08, 2003 - first edition issued 0.92 nov 05, 2003 2 table 1.1 interrupt : revise 10 sources to 11 sources add on power consumption 4 table 1.2 delete ** 6 table 1.3 cnvss and mode : delete ( 5k ?
c-2 revision history rev. date description page summary r8c/11 group hardware manual 0.92 n ov 05, 2003 59 figure 10.9 revise compare 1 to compare 0 and compare 2 to compare 1 62 figure 10.13 tyzmr, tywc bit : revise as function varies depending on the operation mode 64 figure 10.14 tcc1, tcc 12 bit : revise ro to rw 68 figure 11.1 is revised 71 figure 12.1 delete of clr 76 table 12.5 is revised 79 figure 12.10 add notes 7 and revise 0d16 to 0e16 revise some parts in figure 80 figure 12.11 delete of clr 81 figure 12.13 tyzoc notes 1 : revise tys bit to tzs bit typr notes 1 : revise pysc register to tysc register 88 figure 12.18 delete of clr 89 figure 12.20 tyzoc notes 1 : revise tys bit to tzs bit add note 3 95 table 12.11 revised 98 table 12.12 revised 101 figure 12.28 add sampling clock 103 figure 12.31 tm0 and tm1 : add setting range on output compare mode 104 figure 12.32 tcc1, bit 2 : revise ro to rw notes are revised 120 table 13.5 bit ckpol, add set to 0 131 section 14.3 add sentences under the sixth line add figure 14.6 138 figure 15.7 notes 2 and 3 : revise its content is 0 to its content is indeterminate figure 15.8 notes 1 and 2 : revise its content is 0 to its content is indeterminate
c-3 revision history rev. date description page summary r8c/11 group hardware manual 0.92 nov 05, 2003 141 table 16.2 delete notes 3 and 4 142 table 16.3 delete tsamp add figure 16.1 143 revise table 16.4 revise table 16.5 revise table 16.6 add figure 16.2 revise figure 16.2 to figure 16.3 revise figure 16.3, add notes(4) 144 revise table 16.7 146 table 16.10 power supply current : revise vcc = 4.2 to 5.5 v to 3.3 to 5.5 v low-speed on-chip oscillator mode : revise 100 khz to 125 khz high-speed mode and medium-speed mode : delete xin = 5 mhz, add xin = 16 mhz and xin = 10 mhz tbd on high-speed mode and medium-speed mode : add values low-speed on-chip oscillator/wait/stop mode : revise data add vc27= 0 in wait mode 147 add table 16.11 to 16.15 table 16.13 revise notes 1 and 2 148 add figure 16.4 149 table 16.16 notes 1 : revise f(bclk) = 5 mhz to 10 mhz 150 table 16.17 low-speed on-chip oscillator mode : revise 100 khz to 125 khz high-speed mode and medium-speed mode : delete xin = 5 mhz, add xin = 16mhz and xin = 10 mhz tbd on high-speed mode and medium-speed mode : add values low-speed on-chip oscillator/wait/stop mode : revise data add vc27= 0 in wait mode 151 add table 16.18 to 16.22 table 16.20 revise notes 1 and 2
c-4 revision history rev. date description page summary r8c/11 group hardware manual 0.92 nov 05, 2003 152 add figure 16.5 153 delete data retention on table 17.1 154 section 17.2 add under the eighth line 155 add voltage detection on figure 17.2 160 figure 17.4 fmr1, bit 6 : delete when read, its content is indeterminate revise ro to 170 section 17.5 add sentences 171 table 17.7, p46/xin and p47/xout, revise sentences 173 figure 17.13 add notes 3 figure 17.14 add notes 2 178 section 19.3.2 add (1) and (4) add section 19.3.3 (1) revise 19.3.3 timer z to 19.3.4 timer z section 19.3.4 add (1) 184 section 20 add (5) and (6) 0.93 feb 18, 2004 170-173 add 4 pages 1.00 sep 17,2004 all pages words standardized (on-chip oscillator, serial interface, a/d) 2 table 1.1 revised 5 figure 1.3, notes 3 added 6 table 1.3 revised 9 figure 3.1, notes added 10-13 one body sentence in chapter 4 added; titles of table 4.1 to 4.4 added 12 table 4.3 revised; table 4.4 revised 17 in 5.1.2, body sentences added 21 figure 5.8 revised 22 figure 5.9 revised 23 figure 5.10 revised
c-5 revision history rev. date description page summary r8c/11 group hardware manual 1.00 sep 17,2004 24 figure 5.11 revised figure 5.12 revised 25 line 10 in 5.4.1 revised 27 line 5 in 5.4.2 revised one sentence in 5.4.2 deleted table 5.3 revised 29 figure 6.1 revised 30 figure 6.2 revised (cm0 and cm1) 31 figure 6.3 revised 32 figure 6.4 revised (hr0) 38 table 6.3 revised one sentence in pin status in stop mode added 42 one sentence in 6.5.1 moves to chapter 19 60 one body sentence in 10.2.1 added 62 one body sentence in 10.2.3 added 63 one body sentence in 10.2.4 added 64 figure 10.14 revised (tcc1) 65 figure 10.15 revised 68 figure 11.1 revised 71 line 4 in 12.1 revised 74 table 12.3 revised 75 table 12.4 revised 76 figure 12.7 revised 78 table 12.6 revised; figure 12.9 revised 83 table 12.7 revised 85 table 12.8 revised, notes revised 86 figure 12.16, notes added 88 5 line in 12.3 revised; figure 12.18 revised 91 table 12.9 revised 93 table 12.10 revised, notes revised 95 table 12.11 revised, notes revised 97 figure 12.25 revised 98 table 12.12 revised, notes revised 102 figure 12.30 revised 103 figure 12.31 revised (tm1 and tcc0) 104 figure 12.32 revised (tcc1 and tcout) 105 table 12.13 revised 107 table 12.14 revised 108 figure 12.34 revised 110 figure 13.2 revised 118 13.1.3 revised 122 figure 13.10 revised
c-6 revision history rev. date description page summary r8c/11 group hardware manual 1.00 sep 17,2004 132 figure numbers in 15.1.1, 15.1.2, 15.1.3 and 15.1.4 revised 133 figure 15.1 revised (p1 0 to p1 2 ) 140 table 15.1 revised 141 table 16.2 revised 142 table 16.3 revised 143 table 16.4 revised; table 16.5 revised 144 table 16.6, 16.7 and 16.8 revised; figure 16.3 revised 145 table 16.9 revised; table 16.10 revised 147 table 16.12 revised table 16.16 revised 149 table 16.17 revised 151 table 16.19 revised 157 line 2 and 8 in 17.4.2 revised 158 fmr46 bit revised 159 figure 17.3 revised 160 figure 17.4 revised (fmr4) 162 figure 17.7 revised; figure title revised 163 table 17.4 revised 165 figure 17.9 revised 166 figure 17.10 revised 168 table 17.6 revised 175-186 compositions in chapter 19 modified; 19.3 added; 19.4.5 revised; 19.7 revised 187 (7) in chapter 20 added 191 appendix 3 added 192-193 page numbers in register index revised 1.10 apr.27.2005 4 table 1.2, figure 1.2 pa ckage name revised 5 figure 1.3 package name revised 10 table 4.1 revised 12 table 4.3 revised 14 5.1.1 partly revised 15 figure 5.2 partly revised 19 figure 5.6 partly added 21 5.4 partly revised 22 figure 5.8 partly revised 29 table 6.1 partly added 31 figure 6.2 partly revised 32 figure 6.3 partly revised 33 figure 6.4 partly deleted 34 6.1 partly revised 36 6.3.1 partly deleted 37 6.4.1 partly revised 38 table 6.2 partly revised 41 figure 6.6 revised 42 figure 6.7 deleted
c-7 revision history rev. date description page summary r8c/11 group hardware manual 1.10 apr .27.2005 42 6.5 partly deleted table 6.4 partly deleted 6.5.1 partly revised 69 figure 11.2 partly revised 78 figure 12.9 partly revised 95 table 12.11 partly revised 98 table 12.12 partly revised 103 figure12.31 partly revised 120 table 13.6 partly revised 123 13.2.3 bit rate added 132 figure 14.6 partly revised 14.4 added 133 14.5 added 134 14.6 added 136 figure 15.1 revised 137 figure 15.2 revised 138 figure 15.3 revised 139 figure 15.4 revised 143-148 15.2 added 149 table15.24 partly revised figure 15.10 added 151 table 16.3 partly revised 153 table 16.6, 16.7 revised 154 table 16.9, 16.10 partly revised 158 table 16.17 partly revised 163 figure 17.1 revised 170 figure 17.5 added 173 ?rogram command partly revised 175 figure 17.11 partly added 181 figure 17.13 package name revised 183 18.1 partly revised 188 19.3.2 added 189 19.4.4 partly revised 191 19.6 partly revised 192 19.7.1 partly added 196 20 partly revised 197 package dimensions revised 1.20 jan.27.2006 2 t able 1.1 performance outline revised 3 figure 1.1 block diagram partly revised 4 1.4 product information, title of table 1.2 ?roduct list? ?roduct informaton?revised figure 1.2 type no., memory size, and package partly revised 6 table 1.3 pin description timer c revised 7-8 2 central processing unit (cpu) revised figure 2.1 cpu register revised 10 table 4.1 sfr information(1) notes:1 revised 11 table 4.2 sfr information(2) notes:1 revised
c-8 revision history rev. date description page summary r8c/11 group hardware manual 1.20 jan.27.2006 12 table 4.3 sfr information(3); 0081 16 : ?rescaler y? ?rescaler y register 0082 16 : ?imer y secondary ?imer y secondary register 0083 16 : ?imer y primary ?imer y primary register 0085 16 : ?rescaler z ?rescaler z register 0086 16 : ?imer z secondary? ?imer z secondary register 0087 16 : ?imer z primary ?imer z primary register 008c 16 : ?rescaler x? ?rescaler x register?revised notes:1, 2 revised 13 table 4.4 sfr information(4) notes:1 revised 15 figure 5.2 reset sequence; ?2cycles? ?4cycles?revised 18 5.1.3 power-on reset function revised 29 6 clock generation circuit; ?oscillation stop detect function) ?oscillation stop detection function)?revised table 6.1 clock generation circuit specifications notes: 2 deleted 32 figure 6.3 ocd register notes: 3 partly deleted 35 6.2.1 low-speed on-chip oscillator clock; ?he application products ... to accommodate the frequency range.? ?he application products ... for the frequency change.?revised 38 table 6.2 setting clock related bit and modes cm13 added 42 6.5.1 how to use oscillation stop detection function: ?his function cannot ... is below 2 mhz.?added 46 table 9.1 bus cycles for access space, table 9.2 access unit and bus operation; ?fr? ?fr, data flash? rom/ram? ?rogram rom/ram?revised 51 table 10.2 relocatable vector tables; ?/d ?/d conversion?revised 59 figure 10.9 interrupts priority select circuit notes: 1 deleted 71 figure 12.1 timer x block diagram; ?eripheral data bus ?ata bus?revised 74 table 12.3 pulse output mode specifications notes: 1 added 88 figure 12.18 timer z block diagram; ?eripheral data bus? ?ata bus?revised 102 figure 12.30 cmp waveform output unit revised 107 table 12.14 output compare mode specifications notes: 2 revised 108 figure 12.34 operation example of timer c in output compare mode revised 111 figure 13.3 u0tb to u1tb registers, u0rb and u1rb registers, and u0brg and u1brg registers; uarti transmit buffer register (i=0, 1) revised uarti bit rate register (i=0, 1) ; notes: 3 added 112 figure 13.4 u0mr to u1mr registers and u0c0 and u1c0 registers; uarti transmit/receive control register 0 (i=0, 1); notes: 1 added 113 figure 13.5 u0c1 and u1c1 registers and ucon register; uart transmit/receive control register 2; notes: 2 added 120 table 13.5 registers to be used and settings in uart mode; uibrg: ? ? to 7?revised 125 figure 14.1 a/d converter block diagram ?ref? ?com?revised 135 14.7 output impedance of sensor under a/d conversion added 138 figure 15.1 programmable i/o ports (1); notes: 1 added 139 figure 15.2 programmable i/o ports (2); notes: 1 added 140 figure 15.3 programmable i/o ports (3); notes: 1 added 141 figure 15.4 programmable i/o ports (4); notes: 1 added 142 figure 15.5 programmable i/o ports (5); notes: 3 added
c-9 revision history rev. date description page summary r8c/11 group hardware manual 1.20 jan.27.2006 146 table 15.9 port p1 0 /ki 0 /an 8 /cmp0 0 setting; setting value: output port, p1 deleted 147 _____ table 15.10 port p1 1 /ki 1 /an 9 /cmp0 1 setting; setting value: output port, p1 deleted _____ table 15.11 port p1 2 /ki 2 /an 10 /cmp0 2 setting; setting value: output port, p1 deleted 149 table 15.17 port p3 0 /cntr 0 /cmp1 0 setting; p3 deleted table 15.18 port p3 1 /tz out /cmp1 1 setting; p3 deleted _______ table 15.19 port p3 2 /int 2 /cntr 1 /cmp1 2 setting; p3 deleted 150 _______ table 15.20 port p3 3 /int 3 /tc in setting; bit: ?d3_1? ?d3_3 _______ table 15.22 port p4 5 /int 0 setting; ?d3_3? ?d4_5 table 15.23 port x in /p4 6 , x out /p4 7 setting; setting value: external input to x in pin, ??output from x out pin; cm1: ?? ?? cm0: ?? ?? feedback resistance: ?ff? ?n 152 table 16.2 recommended operating conditions; notes: 1, 2, 3 revised 153 table 16.3 a/d conversion characteristics; ?/d operation clock frequency? ?/d operating clock frequency?revised notes: 1, 2, 3, 4 revised 154 table 16.4 flash memory (program rom) electrical characteristics; ?opr? ?mbient temperature?revised measuring condition of byte program time and block erase time deleted 155 table 16.6 reset circuit electrical characteristics (when using hardware reset 2) notes: 3 (vpor1) added 156 table 16.8 high-speed on-chip oscillator circuit electrical characteristics; ?igh-speed on-chip oscillator temperature dependence ?igh-speed on-chip oscillator frequency temperature dependence revised table 16.10 electrical characteristics (1) [v cc =5v]; ?1 0 to p1 7 except x out ? ?xcept p1 0 to p1 7 , x out ?revised 157 table 16.11 electrical characteristics (2) [v cc =5v] notes: 1, 2 revised measuring condition stop mode: ?opr = 25 ??added 160 table 16.17 electrical characteristics (3) [v cc =3v] ?1 0 to p1 7 except x out ? ?xcept p1 0 to p1 7 , x out ?revised 161 table 16.18 electrical characteristics (4) [v cc =3v] notes: 1, 2 revised measuring condition stop mode: ?opr = 25 ??added 165 figure 17.1 flash memory block diagram revised 171 figure 17.4 fmr1 register and fmr4 register; flash memory control register 4 notes: 2 ?ther than this period, this bit is set to ? ??revised 177 figure 17.11 block erase flow chart (when using erase-suspend function); ?rite ?0 16 to the uppermost block address ?rite ?0 16 to the any block address?revised 180 figure 17.12 full status check and handling procedure for each error revised 182 table 17.7 pin functions (flash memory standard serial i/o mode); ____________ reset: revised
c-10 revision history rev. date description page summary r8c/11 group hardware manual 1.20 jan.27.2006 186 19.1.1 stop mode; use the next program to enter stop mode. ?added ? example of entering stop mode? ? program of entering stop mode ?rogram example?deleted 190 19.3.1 oscillation stop detection function ?ince the oscillation stop ... is 2 mhz or below, ...? ?ince the oscillation stop ... is below 2 mhz, ...?revised 200 appendix figure 2.2 connecting examples with m16c flash starter (m3a-0806); notes: 1 revised pulled up added
renesas 16-bit single-chip microcomputer hardware manual r8c/11 group publication data : rev.0.93 feb 18, 2004 rev.1.20 jan 27, 2006 published by : sales strategic planning div. renesas technology corp. ? 2006. renesas technology corp., all rights reserved. printed in japan.
r8c/11 group hardware manual 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan

▲Up To Search▲

Price & Availability of R5F21113DFP

	To Download R5F21113DFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .